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Commit 18bebdf0 authored by Mayank Rana's avatar Mayank Rana
Browse files

ARM: dts: msm: Add cfg_ahb_clk reference with USB3 for msm8996 



cfg_ahb_clk reference is required with USB controller driver to access
AHB2PHY register. Hence add cfg_ahb_clk reference with USB3 device node
for msm8996.

Change-Id: I651371550b001abf8cc1895b7c1a8f959b1e1f53
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 50e0173f

arch/arm/boot/dts/qcom/msm8996.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -1790,10 +1790,11 @@ 
			<&clock_gcc clk_gcc_aggre2_usb3_axi_clk>,

			<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			<&clock_gcc clk_gcc_usb30_sleep_clk>,

			<&clock_gcc clk_cxo_dwc3_clk>;

			<&clock_gcc clk_cxo_dwc3_clk>,

			<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;



		clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk",

				"sleep_clk", "xo";

				"sleep_clk", "xo", "cfg_ahb_clk";



		dwc3@6a00000 {

			compatible = "snps,dwc3";
@@ -1897,9 +1898,10 @@ 
			 <&clock_gcc clk_gcc_usb20_mock_utmi_clk>,

			 <&clock_gcc clk_gcc_usb20_sleep_clk>,

			 <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_cxo_dwc3_clk>;

			 <&clock_gcc clk_cxo_dwc3_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;

		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",

			      "ref_clk", "xo";

			      "ref_clk", "xo", "cfg_ahb_clk";



		dwc3@7600000 {

			compatible = "snps,dwc3";