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Commit 173701d7 authored by Michal Simek's avatar Michal Simek
Browse files

microblaze: Clear all MSR flags on the first kernel instruction 



The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: default avatarMichal Simek <monstr@monstr.eu>
parent cc5647a6

arch/microblaze/kernel/head.S

+2 −3
Original line number Diff line number Diff line
@@ -63,9 +63,7 @@ ENTRY(_start) 
real_start:

#endif



	mfs	r1, rmsr

	andi	r1, r1, ~2

	mts	rmsr, r1

	mts	rmsr, r0

/*

 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'

 * if the msrclr instruction is not enabled. We use this to detect
@@ -73,6 +71,7 @@ real_start: 
 * r8 == 0 - msr instructions are implemented

 * r8 != 0 - msr instructions are not implemented

 */

	mfs	r1, rmsr

	msrclr	r8, 0 /* clear nothing - just read msr for test */

	cmpu	r8, r8, r1 /* r1 must contain msr reg content */