Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 171699f7 authored by Ross Zwisler's avatar Ross Zwisler Committed by H. Peter Anvin
Browse files

x86: Add support for the clflushopt instruction

Add support for the new clflushopt instruction.  This instruction was
announced in the document "Intel Architecture Instruction Set Extensions
Programming Reference" with Ref # 319433-018.

http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf



[ hpa: changed the feature flag to simply X86_FEATURE_CLFLUSHOPT - if
  that is what we want to report in /proc/cpuinfo anyway... ]

Signed-off-by: default avatarRoss Zwisler <ross.zwisler@linux.intel.com>
Link: http://lkml.kernel.org/r/1393441612-19729-2-git-send-email-ross.zwisler@linux.intel.com


Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent c2bc11f1
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -221,6 +221,7 @@
#define X86_FEATURE_RDSEED	(9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX		(9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP	(9*32+20) /* Supervisor Mode Access Prevention */
#define X86_FEATURE_CLFLUSHOPT	(9*32+23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_AVX512PF	(9*32+26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER	(9*32+27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD	(9*32+28) /* AVX-512 Conflict Detection */
+8 −0
Original line number Diff line number Diff line
@@ -191,6 +191,14 @@ static inline void clflush(volatile void *__p)
	asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
}

static inline void clflushopt(volatile void *__p)
{
	alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
		       ".byte 0x66; clflush %P0",
		       X86_FEATURE_CLFLUSHOPT,
		       "+m" (*(volatile char __force *)__p));
}

#define nop() asm volatile ("nop")