Merge "msm: mdss: configure DSI PHY regulator when coming out of idle collapse" (16c22ece) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/video/msm/mdss/msm_mdss_io_8974.c

+47 −10

Original line number	Diff line number	Diff line
		@@ -428,6 +428,8 @@ void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl)
		{
		struct mdss_dsi_ctrl_pdata *sctrl = NULL;
		struct dsi_shared_data *sdata;
		struct mdss_dsi_ctrl_pdata *octrl;
		u32 reg_val = 0;

		if (ctrl == NULL) {
		pr_err("%s: Invalid input data\n", __func__);
		@@ -435,11 +437,7 @@ void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl)
		}

		sdata = ctrl->shared_data;

		if (ctrl == NULL) {
		pr_err("%s: Invalid input data\n", __func__);
		return;
		}
		octrl = mdss_dsi_get_other_ctrl(ctrl);

		if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) {
		if (mdss_dsi_is_ctrl_clk_master(ctrl))
		@@ -448,11 +446,42 @@ void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl)
		return;
		}

		/*
		* For dual dsi case if we do DSI PHY sw reset,
		* this will reset DSI PHY regulators also.
		* Since DSI PHY regulator is shared among both
		* the DSI controllers, we should not do DSI PHY
		* sw reset when the other DSI controller is still
		* active.
		*/
		mutex_lock(&sdata->phy_reg_lock);
		if ((mdss_dsi_is_hw_config_dual(sdata) &&
		(octrl && octrl->is_phyreg_enabled))) {
		/* start phy lane and HW reset */
		reg_val = MIPI_INP(ctrl->ctrl_base + 0x12c);
		reg_val \|= (BIT(16) \| BIT(8));
		MIPI_OUTP(ctrl->ctrl_base + 0x12c, reg_val);
		/* wait for 1ms as per HW design */
		usleep_range(1000, 2000);
		/* ensure phy lane and HW reset starts */
		wmb();
		/* end phy lane and HW reset */
		reg_val = MIPI_INP(ctrl->ctrl_base + 0x12c);
		reg_val &= ~(BIT(16) \| BIT(8));
		MIPI_OUTP(ctrl->ctrl_base + 0x12c, reg_val);
		/* wait for 100us as per HW design */
		usleep_range(100, 200);
		/* ensure phy lane and HW reset ends */
		wmb();
		} else {
		/* start phy sw reset */
		mdss_dsi_ctrl_phy_reset(ctrl);
		if (sctrl)
		mdss_dsi_ctrl_phy_reset(sctrl);

		}
		mutex_unlock(&sdata->phy_reg_lock);

		if ((sdata->hw_rev == MDSS_DSI_HW_REV_103) &&
		!mdss_dsi_is_hw_config_dual(sdata) &&
		mdss_dsi_is_right_ctrl(ctrl)) {
		@@ -950,6 +979,7 @@ static void mdss_dsi_phy_regulator_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
		}

		sdata = ctrl->shared_data;
		other_ctrl = mdss_dsi_get_other_ctrl(ctrl);

		mutex_lock(&sdata->phy_reg_lock);
		if (enable) {
		@@ -961,6 +991,14 @@ static void mdss_dsi_phy_regulator_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
		mdss_dsi_20nm_phy_regulator_enable(ctrl);
		break;
		default:
		/*
		* For dual dsi case, do not reconfigure dsi phy
		* regulator if the other dsi controller is still
		* active.
		*/
		if (!mdss_dsi_is_hw_config_dual(sdata) \|\|
		(other_ctrl && (!other_ctrl->is_phyreg_enabled
		\|\| other_ctrl->mmss_clamp)))
		mdss_dsi_28nm_phy_regulator_enable(ctrl);
		break;
		}
		@@ -974,7 +1012,6 @@ static void mdss_dsi_phy_regulator_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
		*/
		if (mdss_dsi_is_hw_config_split(ctrl->shared_data) \|\|
		mdss_dsi_is_hw_config_dual(ctrl->shared_data)) {
		other_ctrl = mdss_dsi_get_other_ctrl(ctrl);
		if (other_ctrl && !other_ctrl->is_phyreg_enabled)
		mdss_dsi_phy_regulator_disable(ctrl);
		} else {