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Commit 169c3c16 authored by Paul Gortmaker's avatar Paul Gortmaker Committed by Ralf Baechle
Browse files

MIPS: Delete Wind River ppmc eval board support. 



This board has been EOL for many years now; lets not burden people doing
build coverage and other tree wide work with working on essentially dead
files.

[ralf@linux-mips.org: Also remove arch/mips/include/asm/mach-wrppmc/war.h.]

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Patchwork: http://patchwork.linux-mips.org/patch/5503/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5a772eee

arch/mips/Kbuild.platforms

+0 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ platforms += sibyte 
platforms += sni

platforms += txx9

platforms += vr41xx

platforms += wrppmc



# include the platform specific files

include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

arch/mips/Kconfig

+0 −23
Original line number Diff line number Diff line
@@ -712,29 +712,6 @@ config MIKROTIK_RB532 
	  Support the Mikrotik(tm) RouterBoard 532 series,

	  based on the IDT RC32434 SoC.



config WR_PPMC

	bool "Wind River PPMC board"

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_CPU

	select BOOT_ELF32

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select PCI_GT64XXX_PCI0

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_CPU_MIPS64_R1

	select SYS_HAS_CPU_NEVADA

	select SYS_HAS_CPU_RM7000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	help

	  This enables support for the Wind River MIPS32 4KC PPMC evaluation

	  board, which is based on GT64120 bridge chip.



config CAVIUM_OCTEON_SOC

	bool "Cavium Networks Octeon SoC based boards"

	select CEVT_R4K

arch/mips/configs/wrppmc_defconfig

deleted100644 → 0
+0 −97
Original line number Diff line number Diff line 
CONFIG_WR_PPMC=y

CONFIG_HZ_1000=y

CONFIG_EXPERIMENTAL=y

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_BSD_PROCESS_ACCT=y

CONFIG_LOG_BUF_SHIFT=14

CONFIG_BLK_DEV_INITRD=y

# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set

CONFIG_EXPERT=y

CONFIG_KALLSYMS_EXTRA_PASS=y

# CONFIG_EPOLL is not set

CONFIG_SLAB=y

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

CONFIG_MODVERSIONS=y

CONFIG_MODULE_SRCVERSION_ALL=y

CONFIG_PCI=y

CONFIG_HOTPLUG_PCI=y

CONFIG_BINFMT_MISC=y

CONFIG_PM=y

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_XFRM_MIGRATE=y

CONFIG_INET=y

CONFIG_IP_MULTICAST=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

CONFIG_IP_PNP_RARP=y

CONFIG_IP_MROUTE=y

CONFIG_ARPD=y

CONFIG_INET_XFRM_MODE_TRANSPORT=m

CONFIG_INET_XFRM_MODE_TUNNEL=m

CONFIG_INET_XFRM_MODE_BEET=m

CONFIG_TCP_MD5SIG=y

# CONFIG_IPV6 is not set

CONFIG_NETWORK_SECMARK=y

CONFIG_FW_LOADER=m

CONFIG_BLK_DEV_RAM=y

CONFIG_SGI_IOC4=m

CONFIG_NETDEVICES=y

CONFIG_PHYLIB=y

CONFIG_VITESSE_PHY=m

CONFIG_SMSC_PHY=m

CONFIG_NET_ETHERNET=y

CONFIG_NET_PCI=y

CONFIG_E100=y

CONFIG_QLA3XXX=m

CONFIG_CHELSIO_T3=m

CONFIG_NETXEN_NIC=m

# CONFIG_INPUT is not set

# CONFIG_SERIO is not set

# CONFIG_VT is not set

CONFIG_SERIAL_8250=y

CONFIG_SERIAL_8250_CONSOLE=y

CONFIG_SERIAL_8250_NR_UARTS=1

CONFIG_SERIAL_8250_RUNTIME_UARTS=1

# CONFIG_HW_RANDOM is not set

CONFIG_PROC_KCORE=y

CONFIG_TMPFS=y

CONFIG_TMPFS_POSIX_ACL=y

CONFIG_NFS_FS=y

CONFIG_NFS_V3=y

CONFIG_ROOT_NFS=y

CONFIG_DLM=m

CONFIG_CMDLINE_BOOL=y

CONFIG_CMDLINE="console=ttyS0,115200n8"

CONFIG_CRYPTO_NULL=m

CONFIG_CRYPTO_CBC=m

CONFIG_CRYPTO_ECB=m

CONFIG_CRYPTO_LRW=m

CONFIG_CRYPTO_PCBC=m

CONFIG_CRYPTO_XCBC=m

CONFIG_CRYPTO_MD4=m

CONFIG_CRYPTO_MICHAEL_MIC=m

CONFIG_CRYPTO_SHA256=m

CONFIG_CRYPTO_SHA512=m

CONFIG_CRYPTO_TGR192=m

CONFIG_CRYPTO_WP512=m

CONFIG_CRYPTO_ANUBIS=m

CONFIG_CRYPTO_ARC4=m

CONFIG_CRYPTO_BLOWFISH=m

CONFIG_CRYPTO_CAMELLIA=m

CONFIG_CRYPTO_CAST5=m

CONFIG_CRYPTO_CAST6=m

CONFIG_CRYPTO_DES=m

CONFIG_CRYPTO_FCRYPT=m

CONFIG_CRYPTO_KHAZAD=m

CONFIG_CRYPTO_SERPENT=m

CONFIG_CRYPTO_TEA=m

CONFIG_CRYPTO_TWOFISH=m

CONFIG_CRYPTO_DEFLATE=m

CONFIG_CRC_CCITT=y

CONFIG_CRC16=y

CONFIG_LIBCRC32C=y

arch/mips/include/asm/mach-wrppmc/mach-gt64120.h

deleted100644 → 0
+0 −83
Original line number Diff line number Diff line 
/*

 * This is a direct copy of the ev96100.h file, with a global

 * search and replace.	The numbers are the same.

 *

 * The reason I'm duplicating this is so that the 64120/96100

 * defines won't be confusing in the source code.

 */

#ifndef __ASM_MIPS_GT64120_H

#define __ASM_MIPS_GT64120_H



/*

 * This is the CPU physical memory map of PPMC Board:

 *

 *    0x00000000-0x03FFFFFF	 - 64MB SDRAM (SCS[0]#)

 *    0x1C000000-0x1C000000	 - LED (CS0)

 *    0x1C800000-0x1C800007	 - UART 16550 port (CS1)

 *    0x1F000000-0x1F000000	 - MailBox (CS3)

 *    0x1FC00000-0x20000000	 - 4MB Flash (BOOT CS)

 */



#define WRPPMC_SDRAM_SCS0_BASE	0x00000000

#define WRPPMC_SDRAM_SCS0_SIZE	0x04000000



#define WRPPMC_UART16550_BASE	0x1C800000

#define WRPPMC_UART16550_CLOCK	3686400 /* 3.68MHZ */



#define WRPPMC_LED_BASE		0x1C000000

#define WRPPMC_MBOX_BASE	0x1F000000



#define WRPPMC_BOOTROM_BASE	0x1FC00000

#define WRPPMC_BOOTROM_SIZE	0x00400000 /* 4M Flash */



#define WRPPMC_MIPS_TIMER_IRQ	7 /* MIPS compare/count timer interrupt */

#define WRPPMC_UART16550_IRQ	6

#define WRPPMC_PCI_INTA_IRQ	3



/*

 * PCI Bus I/O and Memory resources allocation

 *

 * NOTE: We only have PCI_0 hose interface

 */

#define GT_PCI_MEM_BASE 0x13000000UL

#define GT_PCI_MEM_SIZE 0x02000000UL

#define GT_PCI_IO_BASE	0x11000000UL

#define GT_PCI_IO_SIZE	0x02000000UL



/*

 * PCI interrupts will come in on either the INTA or INTD interrupt lines,

 * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our

 * boards, they all either come in on IntD or they all come in on IntA, they

 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the

 * "requested" interrupt numbers and go through the list whenever we get an

 * IntA/D.

 *

 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and

 * INTD is 11.

 */

#define GT_TIMER	4

#define GT_INTA		2

#define GT_INTD		5



#ifndef __ASSEMBLY__



/*

 * GT64120 internal register space base address

 */

extern unsigned long gt64120_base;



#define GT64120_BASE	(gt64120_base)



/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */

#undef WRPPMC_EARLY_DEBUG



#ifdef WRPPMC_EARLY_DEBUG

extern void wrppmc_led_on(int mask);

extern void wrppmc_led_off(int mask);

extern void wrppmc_early_printk(const char *fmt, ...);

#else

#define wrppmc_early_printk(fmt, ...) do {} while (0)

#endif /* WRPPMC_EARLY_DEBUG */



#endif /* __ASSEMBLY__ */

#endif /* __ASM_MIPS_GT64120_H */

arch/mips/include/asm/mach-wrppmc/war.h

deleted100644 → 0
+0 −24
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>

 */

#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H

#define __ASM_MIPS_MACH_WRPPMC_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	1

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */