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Commit 15eb169b authored by Pawel Moll's avatar Pawel Moll Committed by Will Deacon
Browse files

ARM: proc: add Cortex-A5 proc info 



This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.

Signed-off-by: default avatarPawel Moll <pawel.moll@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent dc939cd8

arch/arm/mm/proc-v7.S

+11 −0
Original line number Diff line number Diff line
@@ -278,6 +278,7 @@ cpu_resume_l1_flags: 
 *	It is assumed that:

 *	- cache type register is implemented

 */

__v7_ca5mp_setup:

__v7_ca9mp_setup:

#ifdef CONFIG_SMP

	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
@@ -443,6 +444,16 @@ __v7_setup_stack: 
	.long	v7_cache_fns

.endm



	/*

	 * ARM Ltd. Cortex A5 processor.

	 */

	.type   __v7_ca5mp_proc_info, #object

__v7_ca5mp_proc_info:

	.long	0x410fc050

	.long	0xff0ffff0

	__v7_proc __v7_ca5mp_setup

	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info



	/*

	 * ARM Ltd. Cortex A9 processor.

	 */