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Commit 15ce5a1d authored by David Keitel's avatar David Keitel
Browse files

soc: qcom: pil-q6v5: Update q6v55 reset sequence 



Update the reset sequence to support qdspv61-1-1 for
mdmcalifornium.

Change-Id: I7c097d571d0048f05f922d34220fc01dfa5ce186
Signed-off-by: default avatarDavid Keitel <dkeitel@codeaurora.org>
parent 5ef36a5b

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ Optional properties: 
- qcom,qdsp6v56-1-8: Boolean- Present if the qdsp version is v56 1.8

- qcom,qdsp6v56-1-8-inrush-current: Boolean- Present if the qdsp version is V56 1.8 and has in-rush

				    current issue.

- qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1



Example:

	qcom,mss@fc880000 {

drivers/soc/qcom/pil-q6v5.c

+45 −2
Original line number Diff line number Diff line
@@ -30,8 +30,10 @@ 
#define QDSP6SS_RESET			0x014

#define QDSP6SS_GFMUX_CTL		0x020

#define QDSP6SS_PWR_CTL			0x030

#define QDSP6SS_STRAP_ACC		0x110

#define QDSP6V6SS_MEM_PWR_CTL		0x034

#define QDSP6SS_BHS_STATUS		0x078

#define QDSP6SS_MEM_PWR_CTL		0x0B0

#define QDSP6SS_STRAP_ACC		0x110



/* AXI Halt Register Offsets */

#define AXI_HALTREQ			0x0
@@ -72,8 +74,10 @@ 
#define L1IU_SLP_NRET_N                 BIT(15)

#define L1DU_SLP_NRET_N                 BIT(14)

#define L2PLRU_SLP_NRET_N               BIT(13)

#define QDSP6v55_BHS_EN_REST_ACK        BIT(0)



#define HALT_CHECK_MAX_LOOPS            (200)

#define BHS_CHECK_MAX_LOOPS             (200)

#define QDSP6SS_XO_CBCR                 (0x0038)



#define QDSP6SS_ACC_OVERRIDE_VAL	0x20
@@ -354,6 +358,21 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
	writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);

	mb();

	udelay(1);



	if (drv->qdsp6v61_1_1) {

		for (i = BHS_CHECK_MAX_LOOPS; i > 0; i--) {

			if (readl_relaxed(drv->reg_base + QDSP6SS_BHS_STATUS)

			    & QDSP6v55_BHS_EN_REST_ACK)

				break;

			udelay(1);

		}

		if (!i) {

			pr_err("%s: BHS_EN_REST_ACK not set!\n", __func__);

			return -ETIMEDOUT;

		}

	}



	/* Put LDO in bypass mode */

	val |= QDSP6v55_LDO_BYP;

	writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);
@@ -424,6 +443,29 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
			 */

			udelay(1);

		}

	} else if (drv->qdsp6v61_1_1) {

		/* Deassert QDSP6 compiler memory clamp */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);

		val &= ~QDSP6v55_CLAMP_QMC_MEM;

		writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);



		/* Deassert memory peripheral sleep and L2 memory standby */

		val |= (Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N);

		writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);



		/* Turn on L1, L2, ETB and JU memories 1 at a time */

		val = readl_relaxed(drv->reg_base +

				QDSP6V6SS_MEM_PWR_CTL);

		for (i = 28; i >= 0; i--) {

			val |= BIT(i);

			writel_relaxed(val, drv->reg_base +

					QDSP6V6SS_MEM_PWR_CTL);

			/*

			 * Wait for 1us for both memory peripheral and

			 * data array to turn on.

			 */

			udelay(1);

		}

	} else {

		/* Turn on memories. */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);
@@ -567,7 +609,8 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
	drv->qdsp6v56_1_8_inrush_current = of_property_read_bool(

						pdev->dev.of_node,

						"qcom,qdsp6v56-1-8-inrush-current");



	drv->qdsp6v61_1_1 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v61-1-1");

	drv->non_elf_image = of_property_read_bool(pdev->dev.of_node,

						"qcom,mba-image-is-not-elf");

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ struct q6v5_data { 
	bool qdsp6v56_1_5;

	bool qdsp6v56_1_8;

	bool qdsp6v56_1_8_inrush_current;

	bool qdsp6v61_1_1;

	bool non_elf_image;

	bool restart_reg_sec;

	bool override_acc;