Merge "USB: phy: Add snapshot of PHY msm usb driver"

MSM SoC HSUSB controllers

MSM SoC HSUSB controllers

EHCI

OTG:

Required properties :

Required properties :

- compatible:	Should contain "qcom,ehci-host"

- compatible : should be "qcom,hsusb-otg"

- regs:			offset and length of the register set in the memory map

- regs : Array of offset and length of the register sets in the memory map

- usb-phy:		phandle for the PHY device

- reg-names : indicates various iomem resources passed by name. The possible

	strings in this field are:

Example EHCI controller device node:

	"core": USB controller register space. (Required)

	"tcsr": TCSR register for routing USB Controller signals to

	ehci: ehci@f9a55000 {

	either picoPHY0 or picoPHY1. (Optional)

		compatible = "qcom,ehci-host";

	"phy_csr": PHY Wrapper CSR register space. Provides register level

		reg = <0xf9a55000 0x400>;

	interface through AHB2PHY for performing PHY related operations

		usb-phy = <&usb_otg>;

	like retention and HV interrupts management.

	};

- interrupts: IRQ line

- interrupt-names: OTG interrupt name(s) referenced in interrupts above

USB PHY with optional OTG:

            HSUSB OTG expects "core_irq" which is IRQ line from CORE and

            optional ones are described in next section.

Required properties:

- qcom,hsusb-otg-phy-type: PHY type can be one of

- compatible:   Should contain:

	    1 - Chipidea PHY (obsolete)

  "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY

	    2 - Synopsis Pico PHY

  "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY

	    3 - Synopsis Femto PHY

	    4 - QUSB ULPI PHY

- regs:         Offset and length of the register set in the memory map

- qcom,hsusb-otg-mode: Operational mode. Can be one of

- interrupts:   interrupt-specifier for the OTG interrupt.

            1 - Peripheral only mode

	    2 - Host only mode

- clocks:       A list of phandle + clock-specifier pairs for the

	    3 - OTG mode

                clocks listed in clock-names

	    Based on the mode, OTG driver registers platform devices for

- clock-names:  Should contain the following:

	    gadget and host.

  "phy"         USB PHY reference clock

- qcom,hsusb-otg-otg-control: OTG control (VBUS and ID notifications)

  "core"        Protocol engine clock

  can be one of

  "iface"       Interface bus clock

  "alt_core"    Protocol engine clock for targets with asynchronous

                reset methodology. (optional)

- vdccx-supply: phandle to the regulator for the vdd supply for

                digital circuit operation.

- v1p8-supply:  phandle to the regulator for the 1.8V supply

- v3p3-supply:  phandle to the regulator for the 3.3V supply

- resets:       A list of phandle + reset-specifier pairs for the

                resets listed in reset-names

- reset-names:  Should contain the following:

  "phy"         USB PHY controller reset

  "link"        USB LINK controller reset

- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of

            1 - PHY control

            1 - PHY control

	    2 - PMIC control

	    2 - PMIC control

	    3 - User control (via debugfs)

- <supply-name>-supply: handle to the regulator device tree node

         Required "supply-name" is "HSUSB_VDDCX" (when voting for VDDCX) or

         "hsusb_vdd_dig" (when voting for VDDCX Corner voltage),

         "HSUSB_1p8-supply" and "HSUSB_3p3-supply".

- qcom,vdd-voltage-level: This property must be a list of three integer

	values (no, min, max) where each value represents either a voltage

	in microvolts or a value corresponding to voltage corner.

- clocks: a list of phandles to the USB clocks. Usage is as per

	Documentation/devicetree/bindings/clock/clock-bindings.txt

- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

	property.

Optional properties:

	Required clocks:

- dr_mode:      One of "host", "peripheral" or "otg". Defaults to "otg"

	"core_clk": USB core clock that is required for data transfers.

	"iface_clk": USB core clock that is required for register access.

- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device

	Optional clocks:

                Mode Eye Diagram test. Start address at which these values will be

	"sleep_clk": PHY sleep clock. Required for interrupts.

                written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as

	"phy_reset_clk": PHY blocks asynchronous reset clock. Required

                "do not overwrite default value at this address".

		for the USB block reset. It is a reset only clock.

                For example: qcom,phy-init-sequence = < -1 0x63 >;

	"phy_por_clk": Reset only clock for asserting/de-asserting

                Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.

		PHY POR signal. Required for overriding PHY parameters.

	"phy_csr_clk": Required for accessing PHY CSR registers through

		AHB2PHY interface.

	"phy_ref_clk": Required when PHY have referance clock,

	"xo": XO clock. The source clock that is used as a reference clock

		to the PHY.

	"bimc_clk", "snoc_clk", "pcnoc_clk": bus voting clocks. Used to

		keep buses at a nominal frequency during USB peripheral

		mode for achieving max throughput.

- qcom,max-nominal-sysclk-rate: Indicates maximum nominal frequency for which

	system clock should be voted whenever streaming mode is enabled.

- qcom,phy-num: Select number of pyco-phy to use, can be one of

Optional properties :

                0 - PHY one, default

- interrupt-names : Optional interrupt resource entries are:

                1 - Second PHY

    "async_irq" : Interrupt from HSPHY for asynchronous wakeup events in LPM.

                Some platforms may have configuration to allow USB

    "pmic_id_irq" : Interrupt from PMIC for external ID pin notification.

                controller work with any of the two HSPHYs present.

    "phy_irq" : Interrupt from PHY. Used for ID detection.

- qcom,hsusb-otg-disable-reset: If present then core is RESET only during

	    init, otherwise core is RESET for every cable disconnect as well

- qcom,hsusb-otg-pnoc-errata-fix: If present then workaround for PNOC

	    performance issue is applied which requires changing the mem-type

	    attribute via VMIDMT.

- qcom,hsusb-otg-default-mode: The default USB mode after boot-up.

  Applicable only when OTG is controlled by user. Can be one of

            0 - None. Low power mode

            1 - Peripheral

	    2 - Host

- qcom,hsusb-otg-phy-init-seq: PHY configuration sequence. val, reg pairs

  terminate with -1

- qcom,hsusb-otg-power-budget: VBUS power budget in mA

  0 will be treated as 500mA

- qcom,hsusb-otg-pclk-src-name: The source of pclk

- Refer to "Documentation/devicetree/bindings/arm/msm/msm-bus.txt" for

  below optional properties:

    - qcom,msm-bus,name

    - qcom,msm-bus,num_cases - There are three valid cases for this: NONE, MAX

		and MIN bandwidth votes. Minimum two cases must be defined for

		both NONE and MAX votes. If MIN vote is different from NONE VOTE

		then specify third case for MIN VOTE. If explicit NOC clock rates

		are not specified then MAX value should be large enough to get

		desired BUS frequencies. In case explicit NOC clock rates are

		specified, peripheral mode bus bandwidth vote should be defined

		to vote for arbitrated bandwidth so that 60MHz frequency is met.

- qcom,vdd-levels: This property must be a list of three integer values

    - qcom,msm-bus,num_paths

                (no, min, max) where each value represents either a voltage

    - qcom,msm-bus,vectors

                in microvolts or a value corresponding to voltage corner.

- qcom,hsusb-otg-lpm-on-dev-suspend: If present then USB enter to

	    low power mode upon receiving bus suspend.

- qcom,hsusb-otg-clk-always-on-workaround: If present then USB core clocks

	    remain active upon receiving bus suspend and USB cable is connected.

	    Used for allowing USB to respond for remote wakup.

- qcom,hsusb-otg-delay-lpm: If present then USB core will wait one second

	after disconnect before entering low power mode.

- <supply-name>-supply: handle to the regulator device tree node.

         Optional "supply-name" is "vbus_otg" to supply vbus in host mode.

- qcom,dp-manual-pullup: If present, vbus is not routed to USB controller/phy

	and controller driver therefore enables pull-up explicitly before

	starting controller using usbcmd run/stop bit.

- qcom,usb2-enable-hsphy2: If present then USB2 controller is connected to 2nd

	HSPHY.

- qcom,hsusb-log2-itc: value of 2^(log2_itc-1) will be used as the

	interrupt threshold (ITC), when log2_itc is between 1 to 7.

- qcom,hsusb-l1-supported: If present, the device supports l1 (Link power

	management).

- qcom,no-selective-suspend: If present selective suspend is disabled on hub ports.

- qcom,hsusb-otg-mpm-dpsehv-int: If present, indicates mpm interrupt to be

	configured for detection of dp line transition during VDD minimization.

- qcom,hsusb-otg-mpm-dmsehv-int: If present, indicates mpm interrupt to be

	configured for detection of dm line transition during VDD minimization.

- pinctrl-names : This should be defined if a target uses gpio and pinctrl framework.

  See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.

  It should specify the names of the configs that pinctrl can install in driver

	Following are the pinctrl config that can be installed

	"hsusb_active" : Active configuration of pins, this should specify active

	config of vddmin gpio (if used) defined in their pin groups.

	"hsusb_sleep" : Disabled configuration of pins, this should specify sleep

	config of vddmin gpio (if used) defined in their pin groups.

- qcom,hsusb-otg-vddmin-gpio = If present, indicates a gpio that will be used

	to supply voltage to the D+ line during VDD minimization and peripheral

	bus suspend. If not exists, then VDD minimization will not be allowed

	during peripheral bus suspend.

- qcom,hsusb-otg-rw-during-lpm-workaround: If present, indicates that remote-

	wakeup during USB low-power mode SW workaround will be applied. When

	this workaround is applied, the PHCD and the FPR bits are written

	to the PORTSC register in the same register write operation.

- qcom,ahb-async-bridge-bypass: If present, indicates that enable AHB2AHB By Pass

	mode with device controller for better throughput. With this mode, USB Core

	runs using PNOC clock and synchronous to it. Hence it is must to have proper

	"qcom,msm-bus,vectors" to have high bus frequency. User shouldn't try to

	enable this feature without proper bus voting. When this feature is enabled,

	it is required to do HW reset during cable disconnect for host mode functionality

	working and hence need to disable qcom,hsusb-otg-disable-reset. With this feature

	enabled, USB HW has to vote for maximum PNOC frequency as USB HW cannot tolerate

	changes in PNOC frequncy which results in USB functionality failure.

- qcom,disable-retention-with-vdd-min: If present don't allow phy retention but allow

	vdd min.

- qcom,usbin-vadc: Corresponding vadc device's phandle to read usbin voltage using VADC.

	This will be used to get value of usb power supply's VOLTAGE_NOW property.

- qcom,usbid-gpio: This corresponds to gpio which is used for USB ID detection.

- qcom,hub-reset-gpio: This corresponds to gpio which is used for HUB reset.

- qcom,sw-sel-gpio: This corresponds to gpio which is used for switch select routing

	of D+/D- between the USB HUB and type B USB jack for peripheral mode.

- qcom,bus-clk-rate: If present, indicates nominal bus frequency to be voted for

	bimc/snoc/pcnoc clock with usb cable connected. If AHB2AHB bypass is enabled,

	pcnoc value should be defined to very large number so that PNOC runs at max

	frequency.

- qcom,phy-dvdd-always-on: If present PHY DVDD is supplied by a always-on

	regulator unlike vddcx/vddmx. PHY can keep D+ pull-up and D+/D-

	pull-down resistors during peripheral and host bus suspend without

	any re-work.

- qcom,emulation: Indicates that we are running on emulation platform.

- qcom,boost-sysclk-with-streaming: If present, enable controller specific

	streaming feature. Also this flag can bump up usb system clock to max in streaming

	mode. This flag enables streaming mode for all compositions and is different from

	streaming-func property defined in android device node. Please refer Doumentation/

	devicetree/bindings/usb/android-dev.txt for details about "streaming-func" property.

- qcom,axi-prefetch-enable: If present, AXI64 interface will be used for transferring data

       to/from DDR by controller.

Example HSUSB OTG controller device node :

Example HSUSB OTG controller device node :

	usb@f9690000 {

		compatible = "qcom,hsusb-otg";

		reg = <0xf9690000 0x400>;

		reg-names = "core";

		interrupts = <134>;

		interrupt-names = "core_irq";

    usb@f9a55000 {

		qcom,hsusb-otg-phy-type = <2>;

        compatible = "qcom,usb-otg-snps";

		qcom,hsusb-otg-mode = <1>;

        reg = <0xf9a55000 0x400>;

		qcom,hsusb-otg-otg-control = <1>;

        interrupts = <0 134 0>;

		qcom,hsusb-otg-disable-reset;

        dr_mode = "peripheral";

		qcom,hsusb-otg-pnoc-errata-fix;

		qcom,hsusb-otg-default-mode = <2>;

        clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,

		qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xffffffff>;

                <&gcc GCC_USB_HS_AHB_CLK>;

		qcom,hsusb-otg-power-budget = <500>;

		qcom,hsusb-otg-pclk-src-name = "dfab_usb_clk";

		qcom,hsusb-otg-lpm-on-dev-suspend;

		qcom,hsusb-otg-clk-always-on-workaround;

		hsusb_vdd_dig-supply = <&pm8226_s1_corner>;

                HSUSB_1p8-supply = <&pm8226_l10>;

                HSUSB_3p3-supply = <&pm8226_l20>;

		qcom,vdd-voltage-level = <1 5 7>;

		qcom,dp-manual-pullup;

		qcom,hsusb-otg-mpm-dpsehv-int = <49>;

		qcom,hsusb-otg-mpm-dmsehv-int = <58>;

		qcom,max-nominal-sysclk-rate;

		qcom,msm-bus,name = "usb2";

		qcom,msm-bus,num_cases = <2>;

		qcom,msm-bus,num_paths = <1>;

		qcom,msm-bus,vectors =

				<87 512 0 0>,

				<87 512 60000000 960000000>;

		pinctrl-names = "hsusb_active","hsusb_sleep";

		pinctrl-0 = <&vddmin_act>;

		pinctrl-0 = <&vddmin_sus>;

		qcom,hsusb-otg-vddmin-gpio = <&pm8019_mpps 6 0>;

		qcom,hsusb-otg-rw-during-lpm-workaround = <1>;

		qcom,disable-retention-with-vdd-min;

		qcom,usbin-vadc = <&pm8226_vadc>;

		qcom,usbid-gpio = <&msm_gpio 110 0>;

	};

        clock-names = "phy", "core", "iface";

MSM HSUSB EHCI controller

        vddcx-supply = <&pm8841_s2_corner>;

Required properties :

        v1p8-supply = <&pm8941_l6>;

- compatible : should be "qcom,ehci-host"

        v3p3-supply = <&pm8941_l24>;

- reg : offset and length of the register set in the memory map

- interrupts: IRQ lines used by this controller

- interrupt-names : Required interrupt resource entries are:

            HSUSB EHCI expects "core_irq" and optionally "async_irq".

- <supply-name>-supply: handle to the regulator device tree node

  Required "supply-name" is either "hsusb_vdd_dig" or "HSUSB_VDDCX"

  "HSUSB_1p8-supply" "HSUSB_3p3-supply".

- qcom,usb2-power-budget: maximum vbus power (in mA) that can be provided.

- qcom,vdd-voltage-level: This property must be a list of five integer

  values (no, 0.5vsuspend, 0.75suspend, min, max) where each value respresents

  either a voltage in microvolts or a value corresponding to voltage corner.

  First value represents value to vote when USB is not at all active, second

  value represents value to vote when target is not connected to dock during low

  power mode, third value represents vlaue to vote when target is connected to dock

  and no peripheral connected over dock during low power mode, fourth value represents

  minimum value to vote when USB is operational, fifth item represents maximum value

  to vote for USB is operational.

        resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;

Optional properties :

        reset-names = "phy", "link";

- qcom,usb2-enable-hsphy2: If present, select second PHY for USB operation.

- pinctrl-names : This should be defined if a target uses pinctrl framework.

  See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.

  It should specify the names of the configs that pinctrl can install in driver

  Following are the pinctrl configs that can be installed

	"ehci_active" : Active configuration of pins, this should specify active

	config defined in pin groups of used gpio's from resume and

	ext-hub-reset.

	"ehci_sleep" : Disabled configuration of pins, this should specify sleep

	config defined in pin groups of used gpio's from resume and

	ext-hub-reset.

- qcom,resume-gpio: if present then peripheral connected to usb controller

  cannot wakeup from XO shutdown using in-band usb bus resume. Use resume

  gpio to wakeup peripheral.

- qcom,ext-hub-reset-gpio: If present then an external HUB is connected to

  the USB host controller and its RESET_N signal is connected to this

  ext-hub-reset-gpio GPIO. It should be driven LOW to RESET the HUB.

- qcom,usb2-enable-uicc: If present, usb2 port will be used for uicc card connection.

- usb-phy: phandle for the PHY device, if described as a separate device tree node

- qcom,pm-qos-latency: This property represents the maximum tolerable CPU latency in

  microsecs, which is used as a vote to keep the CPUs in a high enough power state when

  USB bus is in use (not suspended).

- Refer to "Documentation/devicetree/bindings/arm/msm/msm-bus.txt" for

  below optional properties:

    - qcom,msm-bus,name

    - qcom,msm-bus,num_cases - Two cases (NONE and MAX) for voting are supported.

    - qcom,msm-bus,num_paths

    - qcom,msm-bus,vectors

        qcom,otg-control = <1>;

Example MSM HSUSB EHCI controller device node :

        qcom,phy-init-sequence = < -1 0x63 >;

	ehci: qcom,ehci-host@f9a55000 {

        qcom,vdd-levels = <1 5 7>;

		compatible = "qcom,ehci-host";

		reg = <0xf9a55000 0x400>;

		interrupts = <0 134 0>, <0 140 0>;

		interrupt-names = "core_irq", "async_irq";

		/* If pinctrl is used and ext-hub-reset and resume gpio's are present*/

		pinctrl-names = "ehci_active","ehci_sleep";

		pinctrl-0 = <&ehci_reset_act &resume_act>;

		pinctrl-1 = <&ehci_reset_sus &resume_sus>;

		qcom,resume-gpio = <&msm_gpio 80 0>;

		qcom,ext-hub-reset-gpio = <&msm_gpio 0 0>;

		hsusb_vdd_dig-supply = <&pm8841_s2_corner>;

		HSUSB_1p8-supply = <&pm8941_l6>;

		HSUSB_3p3-supply = <&pm8941_l24>;

		qcom,usb2-enable-hsphy2;

		qcom,usb2-power-budget = <500>;

		qcom,vdd-voltage-level = <1 2 3 5 7>;

		qcom,usb2-enable-uicc;

	};

	};

#ifndef __UAPI_USB_MSM_EXT_CHG_H

#define __UAPI_USB_MSM_EXT_CHG_H

#include <linux/ioctl.h>

#define USB_CHG_BLOCK_ULPI	1

#define USB_CHG_BLOCK_QSCRATCH	2

#define USB_REQUEST_5V		1

#define USB_REQUEST_9V		2

/**

 * struct msm_usb_chg_info - MSM USB charger block details.

 * @chg_block_type: The type of charger block. QSCRATCH/ULPI.

 * @page_offset: USB charger register base may not be aligned to

 *              PAGE_SIZE.  The kernel driver aligns the base

 *              address and use it for memory mapping.  This

 *              page_offset is used by user space to calaculate

 *              the corret charger register base address.

 * @length: The length of the charger register address space.

 */

struct msm_usb_chg_info {

	uint32_t chg_block_type;

	off_t page_offset;

	size_t length;

};

/* Get the MSM USB charger block information */

#define MSM_USB_EXT_CHG_INFO _IOW('M', 0, struct msm_usb_chg_info)

/* Vote against USB hardware low power mode */

#define MSM_USB_EXT_CHG_BLOCK_LPM _IOW('M', 1, int)

/* To tell kernel about voltage being voted */

#define MSM_USB_EXT_CHG_VOLTAGE_INFO _IOW('M', 2, int)

/* To tell kernel about voltage request result */

#define MSM_USB_EXT_CHG_RESULT _IOW('M', 3, int)

/* To tell kernel whether charger connected is external charger or not */

#define MSM_USB_EXT_CHG_TYPE _IOW('M', 4, int)

#endif /* __UAPI_USB_MSM_EXT_CHG_H */