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Commit 155bc27f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'next-samsung-devel-mmc-spi5' of... 

Merge branch 'next-samsung-devel-mmc-spi5' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into samsung/driver
parents 8a44930a 74ac23a3

arch/arm/mach-exynos/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -148,6 +148,11 @@ config EXYNOS4_SETUP_USB_PHY 
	help

	  Common setup code for USB PHY controller



config EXYNOS4_SETUP_SPI

	bool

	help

	  Common setup code for SPI GPIO configurations.



# machine support



if ARCH_EXYNOS4

arch/arm/mach-exynos/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -60,3 +60,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o 
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)	+= setup-keypad.o

obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o

obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)	+= setup-usb-phy.o

obj-$(CONFIG_EXYNOS4_SETUP_SPI)		+= setup-spi.o

arch/arm/mach-exynos/clock.c

+43 −30
Original line number Diff line number Diff line
@@ -1109,36 +1109,6 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.0",

			.enable		= exynos4_clksrc_mask_peril1_ctrl,

			.ctrlbit	= (1 << 16),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.1",

			.enable		= exynos4_clksrc_mask_peril1_ctrl,

			.ctrlbit	= (1 << 20),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.2",

			.enable		= exynos4_clksrc_mask_peril1_ctrl,

			.ctrlbit	= (1 << 24),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_fimg2d",
@@ -1257,6 +1227,42 @@ static struct clksrc_clk clk_sclk_mmc3 = { 
	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },

};



static struct clksrc_clk clk_sclk_spi0 = {

	.clk		= {

		.name		= "sclk_spi",

		.devname		= "s3c64xx-spi.0",

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit		= (1 << 16),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi1 = {

	.clk		= {

		.name		= "sclk_spi",

		.devname		= "s3c64xx-spi.1",

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit		= (1 << 20),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi2 = {

	.clk		= {

		.name		= "sclk_spi",

		.devname		= "s3c64xx-spi.2",

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit		= (1 << 24),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },

};



/* Clock initialization code */

static struct clksrc_clk *sysclks[] = {

	&clk_mout_apll,
@@ -1305,6 +1311,10 @@ static struct clksrc_clk *clksrc_cdev[] = { 
	&clk_sclk_mmc1,

	&clk_sclk_mmc2,

	&clk_sclk_mmc3,

	&clk_sclk_spi0,

	&clk_sclk_spi1,

	&clk_sclk_spi2,



};



static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1318,6 +1328,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { 
	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),

	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),

	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),

};



static int xtal_rate;

arch/arm/mach-exynos/include/mach/irqs.h

+3 −0
Original line number Diff line number Diff line
@@ -72,6 +72,9 @@ 
#define IRQ_IIC5		IRQ_SPI(63)

#define IRQ_IIC6		IRQ_SPI(64)

#define IRQ_IIC7		IRQ_SPI(65)

#define IRQ_SPI0		IRQ_SPI(66)

#define IRQ_SPI1		IRQ_SPI(67)

#define IRQ_SPI2		IRQ_SPI(68)



#define IRQ_USB_HOST		IRQ_SPI(70)

#define IRQ_USB_HSOTG		IRQ_SPI(71)

arch/arm/mach-exynos/include/mach/map.h

+7 −0
Original line number Diff line number Diff line
@@ -87,6 +87,10 @@ 
#define EXYNOS4_PA_SYSMMU_TV		0x12E20000

#define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000

#define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000

#define EXYNOS4_PA_SPI0			0x13920000

#define EXYNOS4_PA_SPI1			0x13930000

#define EXYNOS4_PA_SPI2			0x13940000





#define EXYNOS4_PA_GPIO1		0x11400000

#define EXYNOS4_PA_GPIO2		0x11000000
@@ -148,6 +152,9 @@ 
#define S3C_PA_RTC			EXYNOS4_PA_RTC

#define S3C_PA_WDT			EXYNOS4_PA_WATCHDOG

#define S3C_PA_UART			EXYNOS4_PA_UART

#define S3C_PA_SPI0			EXYNOS4_PA_SPI0

#define S3C_PA_SPI1			EXYNOS4_PA_SPI1

#define S3C_PA_SPI2			EXYNOS4_PA_SPI2



#define S5P_PA_CHIPID			EXYNOS4_PA_CHIPID

#define S5P_PA_EHCI			EXYNOS4_PA_EHCI