Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 153b4b95 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Convert straggling MCHBAR registers 



All our registers which are written through the MCHBAR are defined
descriptively as an offset to the MCHBAR. We had 3 outliers here.
Convert these as well so all registers which are offsets are MCHBAR can
be easily identified/found within the code.

With this, convert DCLK to also follow this format.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d538bbdf

drivers/gpu/drm/i915/i915_reg.h

+4 −4
Original line number Diff line number Diff line
@@ -1476,7 +1476,7 @@ 
#define MCHBAR_MIRROR_BASE_SNB	0x140000



/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */

#define DCLK 0x5e04

#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)



/** 915-945 and GM965 MCH register controlling DRAM channel access */

#define DCC			0x10200
@@ -1771,9 +1771,9 @@ 
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7

#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))



#define GEN6_GT_PERF_STATUS	0x145948

#define GEN6_RP_STATE_LIMITS	0x145994

#define GEN6_RP_STATE_CAP	0x145998

#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)

#define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)

#define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)



/*

 * Logical Context regs

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -3915,7 +3915,7 @@ void gen6_update_ring_freq(struct drm_device *dev) 
	/* Convert from kHz to MHz */

	max_ia_freq /= 1000;



	min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;

	min_ring_freq = I915_READ(DCLK) & 0xf;

	/* convert DDR frequency from units of 266.6MHz to bandwidth */

	min_ring_freq = mult_frac(min_ring_freq, 8, 3);