Loading arch/arm/boot/dts/qcom/mdmcalifornium-pinctrl.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -337,6 +337,18 @@ bias-pull-down; }; }; pcie0_mdm2apstatus_default: pcie0_mdm2apstatus_default { mux { pins = "gpio16"; function = "gpio"; }; config { pins = "gpio16"; drive-strength = <2>; bias-pull-down; }; }; }; /* UART HS CONFIGURATION */ Loading arch/arm/boot/dts/qcom/mdmcalifornium.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -452,11 +452,12 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; &pcie0_wake_default &pcie0_mdm2apstatus_default>; perst-gpio = <&tlmm_pinmux 65 0>; wake-gpio = <&tlmm_pinmux 61 0>; clkreq-gpio = <&tlmm_pinmux 64 0>; mdm2apstatus-gpio = <&tlmm_pinmux 16 0>; gdsc-vdd-supply = <&gdsc_pcie>; vreg-1.8-supply = <&pmdcalifornium_l5>; Loading Loading
arch/arm/boot/dts/qcom/mdmcalifornium-pinctrl.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -337,6 +337,18 @@ bias-pull-down; }; }; pcie0_mdm2apstatus_default: pcie0_mdm2apstatus_default { mux { pins = "gpio16"; function = "gpio"; }; config { pins = "gpio16"; drive-strength = <2>; bias-pull-down; }; }; }; /* UART HS CONFIGURATION */ Loading
arch/arm/boot/dts/qcom/mdmcalifornium.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -452,11 +452,12 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; &pcie0_wake_default &pcie0_mdm2apstatus_default>; perst-gpio = <&tlmm_pinmux 65 0>; wake-gpio = <&tlmm_pinmux 61 0>; clkreq-gpio = <&tlmm_pinmux 64 0>; mdm2apstatus-gpio = <&tlmm_pinmux 16 0>; gdsc-vdd-supply = <&gdsc_pcie>; vreg-1.8-supply = <&pmdcalifornium_l5>; Loading