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Commit 14211e2f authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge tag 'omap-devel-e-for-3.9' of... 

Merge tag 'omap-devel-e-for-3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.9/clock

Some miscellaneous OMAP2+ clock fixes, mostly related to the recent
common clock framework conversion.

Basic test logs are available here:

    http://www.pwsan.com/omap/testlogs/clock_devel_a_3.9/20130208120108/
parents 88b62b91 b5596a89

arch/arm/mach-omap2/cclock33xx_data.c

+6 −4
Original line number Diff line number Diff line
@@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); 
 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2

 * and ALT_CLK1/2)

 */

DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,

		   AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,

		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);

DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,

		   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,

		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);



/* DPLL_PER */

static struct dpll_data dpll_per_dd = {
@@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = { 
	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,

};



DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);

DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,

			gpio_fck_ops, CLK_SET_RATE_PARENT);



DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);

arch/arm/mach-omap2/cclock3xxx_data.c

+9 −1
Original line number Diff line number Diff line
@@ -426,6 +426,7 @@ static struct clk dpll4_m5x2_ck_3630 = { 
	.parent_names	= dpll4_m5x2_ck_parent_names,

	.num_parents	= ARRAY_SIZE(dpll4_m5x2_ck_parent_names),

	.ops		= &dpll4_m5x2_ck_3630_ops,

	.flags		= CLK_SET_RATE_PARENT,

};



static struct clk cam_mclk;
@@ -443,7 +444,14 @@ static struct clk_hw_omap cam_mclk_hw = { 
	.clkdm_name	= "cam_clkdm",

};



DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);

static struct clk cam_mclk = {

	.name		= "cam_mclk",

	.hw		= &cam_mclk_hw.hw,

	.parent_names	= cam_mclk_parent_names,

	.num_parents	= ARRAY_SIZE(cam_mclk_parent_names),

	.ops		= &aes2_ick_ops,

	.flags		= CLK_SET_RATE_PARENT,

};



static const struct clksel_rate clkout2_src_core_rates[] = {

	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },

arch/arm/mach-omap2/cclock44xx_data.c

+12 −1
Original line number Diff line number Diff line
@@ -595,15 +595,26 @@ static const char *dpll_usb_ck_parents[] = { 


static struct clk dpll_usb_ck;



static const struct clk_ops dpll_usb_ck_ops = {

	.enable		= &omap3_noncore_dpll_enable,

	.disable	= &omap3_noncore_dpll_disable,

	.recalc_rate	= &omap3_dpll_recalc,

	.round_rate	= &omap2_dpll_round_rate,

	.set_rate	= &omap3_noncore_dpll_set_rate,

	.get_parent	= &omap2_init_dpll_parent,

	.init		= &omap2_init_clk_clkdm,

};



static struct clk_hw_omap dpll_usb_ck_hw = {

	.hw = {

		.clk = &dpll_usb_ck,

	},

	.dpll_data	= &dpll_usb_dd,

	.clkdm_name	= "l3_init_clkdm",

	.ops		= &clkhwops_omap3_dpll,

};



DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);

DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);



static const char *dpll_usb_clkdcoldo_ck_parents[] = {

	"dpll_usb_ck",

arch/arm/mach-omap2/clock.h

+11 −0
Original line number Diff line number Diff line
@@ -65,6 +65,17 @@ struct clockdomain; 
		.ops = &_clkops_name,				\

	};



#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name,	\

				_clkops_name, _flags)		\

	static struct clk _name = {				\

		.name = #_name,					\

		.hw = &_name##_hw.hw,				\

		.parent_names = _parent_array_name,		\

		.num_parents = ARRAY_SIZE(_parent_array_name),	\

		.ops = &_clkops_name,				\

		.flags = _flags,				\

	};



#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name)		\

	static struct clk_hw_omap _name##_hw = {		\

		.hw = {						\

arch/arm/mach-omap2/dpll3xxx.c

+3 −2
Original line number Diff line number Diff line
@@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 
		if (dd->last_rounded_rate == 0)

			return -EINVAL;



		/* No freqsel on OMAP4 and OMAP3630 */

		if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {

		/* No freqsel on AM335x, OMAP4 and OMAP3630 */

		if (!soc_is_am33xx() && !cpu_is_omap44xx() &&

		    !cpu_is_omap3630()) {

			freqsel = _omap3_dpll_compute_freqsel(clk,

						dd->last_rounded_n);

			WARN_ON(!freqsel);