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Commit 141fa40c authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
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[ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem 



Patch from Catalin Marinas

ARM1136 erratum 371025 (category 2) specifies that, under rare
conditions, an invalidate I-cache by MVA (line or range) operation can
fail to invalidate a cache line. The recommended workaround is to
either invalidate the entire I-cache or invalidate the range by
set/way rather than MVA.

Note that for a 16K cache size, invalidating a 4K page by set/way is
equivalent to invalidating the entire I-cache.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e7fcdb79

arch/arm/mm/cache-v6.S

+4 −3
Original line number Diff line number Diff line
@@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range) 
#ifdef HARVARD_CACHE

	bic	r0, r0, #CACHE_LINE_SIZE - 1

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D line

	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I line

	add	r0, r0, #CACHE_LINE_SIZE

	cmp	r0, r1

	blo	1b

#endif

	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB

#ifdef HARVARD_CACHE

	mov	r0, #0

#ifdef HARVARD_CACHE

	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer

	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate

#else

	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB

#endif

	mov	pc, lr

arch/arm/mm/flush.c

+4 −2
Original line number Diff line number Diff line
@@ -24,14 +24,16 @@ 
static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)

{

	unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);

	const int zero = 0;



	set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));

	flush_tlb_kernel_page(to);



	asm(	"mcrr	p15, 0, %1, %0, c14\n"

	"	mcrr	p15, 0, %1, %0, c5\n"

	"	mcr	p15, 0, %2, c7, c10, 4\n"

	"	mcr	p15, 0, %2, c7, c5, 0\n"

	    :

	    : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)

	    : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)

	    : "cc");

}