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Commit 1400eb65 authored by Gregory Fong's avatar Gregory Fong Committed by Ralf Baechle
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MIPS: r4k,octeon,r2300: stack protector: change canary per task 



For non-SMP, uses the new random canary value that is stored in the
task struct whenever a new task is forked.  Based on ARM version in
df0698be and subject to the same
limitations: the variable GCC expects, __stack_chk_guard, is global,
so this will not work on SMP.

Quoting Nicolas Pitre <nico@fluxnic.net>: "One way to overcome this
GCC limitation would be to locate the __stack_chk_guard variable into
a memory page of its own for each CPU, and then use TLB locking to
have each CPU see its own page at the same virtual address for each of
them."

Signed-off-by: default avatarGregory Fong <gregory.0xf0@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5488/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 36ecafc5

arch/mips/kernel/asm-offsets.c

+3 −0
Original line number Diff line number Diff line
@@ -82,6 +82,9 @@ void output_task_defines(void) 
	OFFSET(TASK_FLAGS, task_struct, flags);

	OFFSET(TASK_MM, task_struct, mm);

	OFFSET(TASK_PID, task_struct, pid);

#if defined(CONFIG_CC_STACKPROTECTOR)

	OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);

#endif

	DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));

	BLANK();

}

arch/mips/kernel/octeon_switch.S

+7 −0
Original line number Diff line number Diff line
@@ -71,6 +71,13 @@ 
	mtc0	t0, $11,7	/* CvmMemCtl */

#endif

3:



#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)

	PTR_L	t8, __stack_chk_guard

	LONG_L	t9, TASK_STACK_CANARY(a1)

	LONG_S	t9, 0(t8)

#endif



	/*

	 * The order of restoring the registers takes care of the race

	 * updating $28, $29 and kernelsp without disabling ints.

arch/mips/kernel/r2300_switch.S

+7 −0
Original line number Diff line number Diff line
@@ -65,6 +65,13 @@ LEAF(resume) 
	fpu_save_single a0, t0			# clobbers t0



1:



#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)

	PTR_L	t8, __stack_chk_guard

	LONG_L	t9, TASK_STACK_CANARY(a1)

	LONG_S	t9, 0(t8)

#endif



	/*

	 * The order of restoring the registers takes care of the race

	 * updating $28, $29 and kernelsp without disabling ints.

arch/mips/kernel/r4k_switch.S

+6 −0
Original line number Diff line number Diff line
@@ -68,6 +68,12 @@ 
						# clobbers t1

1:



#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)

	PTR_L	t8, __stack_chk_guard

	LONG_L	t9, TASK_STACK_CANARY(a1)

	LONG_S	t9, 0(t8)

#endif



	/*

	 * The order of restoring the registers takes care of the race

	 * updating $28, $29 and kernelsp without disabling ints.