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Commit 13cba4c8 authored by Mayank Rana's avatar Mayank Rana Committed by Matt Wagantall
Browse files

ARM: dts: msm: Add EFUSE configuration with QUSB PHYs for 8996 



EFUSE based register is being used to get QUSB PHY related
TUNE2 parameter's high nibble. Hence pass EFUSE based register
address, number of bits and starting bit position to read
high nibble to confiure both primary and secondary QUSB PHY's
tune2 parameter.

CRs-Fixed: 705188
Change-Id: Ia8c85d12df88b607b29c8b05f29bb7550a421651
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent a11489df

arch/arm/boot/dts/qcom/msm8996.dtsi

+12 −4
Original line number Diff line number Diff line
@@ -1990,13 +1990,17 @@ 
	qusb_phy0: qusb@7411000 {

		compatible = "qcom,qusb2phy";

		reg = <0x07411000 0x180>,

			<0x06af8800 0x400>;

			<0x06af8800 0x400>,

			<0x0007024C 0x4>;

		reg-names = "qusb_phy_base",

			"qscratch_base";

			"qscratch_base",

			"tune2_efuse_addr";

		vdd-supply = <&pm8994_s2_corner>;

		vdda18-supply = <&pm8994_l12>;

		vdda33-supply = <&pm8994_l24>;

		qcom,vdd-voltage-level = <1 5 7>;

		qcom,tune2-efuse-bit-pos = <21>;

		qcom,tune2-efuse-num-bits = <4>;

		qcom,qusb-phy-init-seq = <0xF8 0x80

					0x93 0x84

					0x93 0x88
@@ -2017,13 +2021,17 @@ 
	qusb_phy1: qusb@7412000 {

		compatible = "qcom,qusb2phy";

		reg = <0x07412000 0x180>,

			<0x076f8800 0x400>;

			<0x076f8800 0x400>,

			<0x0007024C 0x4>;

		reg-names = "qusb_phy_base",

			"qscratch_base";

			"qscratch_base",

			"tune2_efuse_addr";

		vdd-supply = <&pm8994_s2_corner>;

		vdda18-supply = <&pm8994_l12>;

		vdda33-supply = <&pm8994_l24>;

		qcom,vdd-voltage-level = <1 5 7>;

		qcom,tune2-efuse-bit-pos = <25>;

		qcom,tune2-efuse-num-bits = <4>;

		qcom,qusb-phy-init-seq = <0xF8 0x80

					0x93 0x84

					0x93 0x88