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Commit 13c6c532 authored by Jan Beulich's avatar Jan Beulich Committed by Ingo Molnar
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x86, 32-bit: also use cpuinfo_x86's x86_{phys,virt}_bits members 



Impact: 32/64-bit consolidation

In a first step, this allows fixing phys_addr_valid() for PAE (which
until now reported all addresses to be valid). Subsequently, this will
also allow simplifying some MTRR handling code.

Signed-off-by: default avatarJan Beulich <jbeulich@novell.com>
LKML-Reference: <49B9101E.76E4.0078.0@novell.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 46d50c98

arch/x86/include/asm/processor.h

+1 −1
Original line number Diff line number Diff line
@@ -75,9 +75,9 @@ struct cpuinfo_x86 { 
#else

	/* Number of 4K pages in DTLB/ITLB combined(in pages): */

	int			x86_tlbsize;

#endif

	__u8			x86_virt_bits;

	__u8			x86_phys_bits;

#endif

	/* CPUID returned core id bits: */

	__u8			x86_coreid_bits;

	/* Max extended CPUID function supported: */

arch/x86/kernel/cpu/common.c

+11 −1
Original line number Diff line number Diff line
@@ -549,13 +549,15 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 
		}

	}



#ifdef CONFIG_X86_64

	if (c->extended_cpuid_level >= 0x80000008) {

		u32 eax = cpuid_eax(0x80000008);



		c->x86_virt_bits = (eax >> 8) & 0xff;

		c->x86_phys_bits = eax & 0xff;

	}

#ifdef CONFIG_X86_32

	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))

		c->x86_phys_bits = 36;

#endif



	if (c->extended_cpuid_level >= 0x80000007)
@@ -602,8 +604,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) 
{

#ifdef CONFIG_X86_64

	c->x86_clflush_size = 64;

	c->x86_phys_bits = 36;

	c->x86_virt_bits = 48;

#else

	c->x86_clflush_size = 32;

	c->x86_phys_bits = 32;

	c->x86_virt_bits = 32;

#endif

	c->x86_cache_alignment = c->x86_clflush_size;
@@ -726,9 +732,13 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 
	c->x86_coreid_bits = 0;

#ifdef CONFIG_X86_64

	c->x86_clflush_size = 64;

	c->x86_phys_bits = 36;

	c->x86_virt_bits = 48;

#else

	c->cpuid_level = -1;	/* CPUID not detected */

	c->x86_clflush_size = 32;

	c->x86_phys_bits = 32;

	c->x86_virt_bits = 32;

#endif

	c->x86_cache_alignment = c->x86_clflush_size;

	memset(&c->x86_capability, 0, sizeof c->x86_capability);

arch/x86/kernel/cpu/intel.c

+5 −0
Original line number Diff line number Diff line
@@ -54,6 +54,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
		c->x86_cache_alignment = 128;

#endif



	/* CPUID workaround for 0F33/0F34 CPU */

	if (c->x86 == 0xF && c->x86_model == 0x3

	    && (c->x86_mask == 0x3 || c->x86_mask == 0x4))

		c->x86_phys_bits = 36;



	/*

	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate

	 * with P/T states and does not stop in deep C-states

arch/x86/mm/ioremap.c

+8 −9
Original line number Diff line number Diff line
@@ -22,13 +22,17 @@ 
#include <asm/pgalloc.h>

#include <asm/pat.h>



#ifdef CONFIG_X86_64



static inline int phys_addr_valid(unsigned long addr)

static inline int phys_addr_valid(resource_size_t addr)

{

	return addr < (1UL << boot_cpu_data.x86_phys_bits);

#ifdef CONFIG_PHYS_ADDR_T_64BIT

	return !(addr >> boot_cpu_data.x86_phys_bits);

#else

	return 1;

#endif

}



#ifdef CONFIG_X86_64



unsigned long __phys_addr(unsigned long x)

{

	if (x >= __START_KERNEL_map) {
@@ -65,11 +69,6 @@ EXPORT_SYMBOL(__virt_addr_valid); 


#else



static inline int phys_addr_valid(unsigned long addr)

{

	return 1;

}



#ifdef CONFIG_DEBUG_VIRTUAL

unsigned long __phys_addr(unsigned long x)

{