Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma (12ff47e7) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/dmaengine.txt

+164 −70

Original line number	Diff line number	Diff line
		@@ -10,17 +10,19 @@ NOTE: For DMA Engine usage in async_tx please see:
		Below is a guide to device driver writers on how to use the Slave-DMA API of the
		DMA Engine. This is applicable only for slave DMA usage only.

		The slave DMA usage consists of following steps
		The slave DMA usage consists of following steps:
		1. Allocate a DMA slave channel
		2. Set slave and controller specific parameters
		3. Get a descriptor for transaction
		4. Submit the transaction and wait for callback notification
		4. Submit the transaction
		5. Issue pending requests and wait for callback notification

		1. Allocate a DMA slave channel
		Channel allocation is slightly different in the slave DMA context, client
		drivers typically need a channel from a particular DMA controller only and even
		in some cases a specific channel is desired. To request a channel
		dma_request_channel() API is used.

		Channel allocation is slightly different in the slave DMA context,
		client drivers typically need a channel from a particular DMA
		controller only and even in some cases a specific channel is desired.
		To request a channel dma_request_channel() API is used.

		Interface:
		struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
		@@ -29,68 +31,160 @@ struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
		where dma_filter_fn is defined as:
		typedef bool (dma_filter_fn)(struct dma_chan chan, void *filter_param);

		When the optional 'filter_fn' parameter is set to NULL dma_request_channel
		simply returns the first channel that satisfies the capability mask. Otherwise,
		when the mask parameter is insufficient for specifying the necessary channel,
		the filter_fn routine can be used to disposition the available channels in the
		system. The filter_fn routine is called once for each free channel in the
		system. Upon seeing a suitable channel filter_fn returns DMA_ACK which flags
		that channel to be the return value from dma_request_channel. A channel
		allocated via this interface is exclusive to the caller, until
		dma_release_channel() is called.
		The 'filter_fn' parameter is optional, but highly recommended for
		slave and cyclic channels as they typically need to obtain a specific
		DMA channel.

		When the optional 'filter_fn' parameter is NULL, dma_request_channel()
		simply returns the first channel that satisfies the capability mask.

		Otherwise, the 'filter_fn' routine will be called once for each free
		channel which has a capability in 'mask'. 'filter_fn' is expected to
		return 'true' when the desired DMA channel is found.

		A channel allocated via this interface is exclusive to the caller,
		until dma_release_channel() is called.

		2. Set slave and controller specific parameters
		Next step is always to pass some specific information to the DMA driver. Most of
		the generic information which a slave DMA can use is in struct dma_slave_config.
		It allows the clients to specify DMA direction, DMA addresses, bus widths, DMA
		burst lengths etc. If some DMA controllers have more parameters to be sent then
		they should try to embed struct dma_slave_config in their controller specific
		structure. That gives flexibility to client to pass more parameters, if
		required.

		Next step is always to pass some specific information to the DMA
		driver. Most of the generic information which a slave DMA can use
		is in struct dma_slave_config. This allows the clients to specify
		DMA direction, DMA addresses, bus widths, DMA burst lengths etc
		for the peripheral.

		If some DMA controllers have more parameters to be sent then they
		should try to embed struct dma_slave_config in their controller
		specific structure. That gives flexibility to client to pass more
		parameters, if required.

		Interface:
		int dmaengine_slave_config(struct dma_chan *chan,
		struct dma_slave_config *config)

		Please see the dma_slave_config structure definition in dmaengine.h
		for a detailed explaination of the struct members. Please note
		that the 'direction' member will be going away as it duplicates the
		direction given in the prepare call.

		3. Get a descriptor for transaction

		For slave usage the various modes of slave transfers supported by the
		DMA-engine are:

		slave_sg - DMA a list of scatter gather buffers from/to a peripheral
		dma_cyclic - Perform a cyclic DMA operation from/to a peripheral till the
		operation is explicitly stopped.
		The non NULL return of this transfer API represents a "descriptor" for the given
		transaction.

		A non-NULL return of this transfer API represents a "descriptor" for
		the given transaction.

		Interface:
		struct dma_async_tx_descriptor (chan->device->device_prep_dma_sg)(
		struct dma_chan *chan,
		struct scatterlist *dst_sg, unsigned int dst_nents,
		struct scatterlist *src_sg, unsigned int src_nents,
		struct dma_async_tx_descriptor (chan->device->device_prep_slave_sg)(
		struct dma_chan chan, struct scatterlist sgl,
		unsigned int sg_len, enum dma_data_direction direction,
		unsigned long flags);

		struct dma_async_tx_descriptor (chan->device->device_prep_dma_cyclic)(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
		size_t period_len, enum dma_data_direction direction);

		4. Submit the transaction and wait for callback notification
		To schedule the transaction to be scheduled by dma device, the "descriptor"
		returned in above (3) needs to be submitted.
		To tell the dma driver that a transaction is ready to be serviced, the
		descriptor->submit() callback needs to be invoked. This chains the descriptor to
		the pending queue.
		The peripheral driver is expected to have mapped the scatterlist for
		the DMA operation prior to calling device_prep_slave_sg, and must
		keep the scatterlist mapped until the DMA operation has completed.
		The scatterlist must be mapped using the DMA struct device. So,
		normal setup should look like this:

		nr_sg = dma_map_sg(chan->device->dev, sgl, sg_len);
		if (nr_sg == 0)
		/* error */

		desc = chan->device->device_prep_slave_sg(chan, sgl, nr_sg,
		direction, flags);

		Once a descriptor has been obtained, the callback information can be
		added and the descriptor must then be submitted. Some DMA engine
		drivers may hold a spinlock between a successful preparation and
		submission so it is important that these two operations are closely
		paired.

		Note:
		Although the async_tx API specifies that completion callback
		routines cannot submit any new operations, this is not the
		case for slave/cyclic DMA.

		For slave DMA, the subsequent transaction may not be available
		for submission prior to callback function being invoked, so
		slave DMA callbacks are permitted to prepare and submit a new
		transaction.

		For cyclic DMA, a callback function may wish to terminate the
		DMA via dmaengine_terminate_all().

		Therefore, it is important that DMA engine drivers drop any
		locks before calling the callback function which may cause a
		deadlock.

		Note that callbacks will always be invoked from the DMA
		engines tasklet, never from interrupt context.

		4. Submit the transaction

		Once the descriptor has been prepared and the callback information
		added, it must be placed on the DMA engine drivers pending queue.

		Interface:
		dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)

		This returns a cookie can be used to check the progress of DMA engine
		activity via other DMA engine calls not covered in this document.

		dmaengine_submit() will not start the DMA operation, it merely adds
		it to the pending queue. For this, see step 5, dma_async_issue_pending.

		5. Issue pending DMA requests and wait for callback notification

		The transactions in the pending queue can be activated by calling the
		issue_pending API. If channel is idle then the first transaction in queue is
		started and subsequent ones queued up.
		On completion of the DMA operation the next in queue is submitted and a tasklet
		triggered. The tasklet would then call the client driver completion callback
		routine for notification, if set.
		issue_pending API. If channel is idle then the first transaction in
		queue is started and subsequent ones queued up.

		On completion of each DMA operation, the next in queue is started and
		a tasklet triggered. The tasklet will then call the client driver
		completion callback routine for notification, if set.

		Interface:
		void dma_async_issue_pending(struct dma_chan *chan);

		==============================================================================
		Further APIs:

		1. int dmaengine_terminate_all(struct dma_chan *chan)

		This causes all activity for the DMA channel to be stopped, and may
		discard data in the DMA FIFO which hasn't been fully transferred.
		No callback functions will be called for any incomplete transfers.

		2. int dmaengine_pause(struct dma_chan *chan)

		This pauses activity on the DMA channel without data loss.

		3. int dmaengine_resume(struct dma_chan *chan)

		Resume a previously paused DMA channel. It is invalid to resume a
		channel which is not currently paused.

		4. enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
		dma_cookie_t cookie, dma_cookie_t last, dma_cookie_t used)

		This can be used to check the status of the channel. Please see
		the documentation in include/linux/dmaengine.h for a more complete
		description of this API.

		This can be used in conjunction with dma_async_is_complete() and
		the cookie returned from 'descriptor->submit()' to check for
		completion of a specific DMA transaction.

		Additional usage notes for dma driver writers
		1/ Although DMA engine specifies that completion callback routines cannot submit
		any new operations, but typically for slave DMA subsequent transaction may not
		be available for submit prior to callback routine being called. This requirement
		is not a requirement for DMA-slave devices. But they should take care to drop
		the spin-lock they might be holding before calling the callback routine
		Note:
		Not all DMA engine drivers can return reliable information for
		a running DMA channel. It is recommended that DMA engine users
		pause or stop (via dmaengine_terminate_all) the channel before
		using this API.

drivers/dma/TODO

+0 −1

Original line number	Diff line number	Diff line
		@@ -9,6 +9,5 @@ TODO for slave dma
		- mxs-dma.c
		- dw_dmac
		- intel_mid_dma
		- ste_dma40
		4. Check other subsystems for dma drivers and merge/move to dmaengine
		5. Remove dma_slave_config's dma direction.

drivers/dma/amba-pl08x.c

+124 −122

Original line number	Diff line number	Diff line
		@@ -156,14 +156,10 @@ struct pl08x_driver_data {
		#define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
		#define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)

		/* Minimum period between work queue runs */
		#define PL08X_WQ_PERIODMIN 20

		/* Size (bytes) of each LLI buffer allocated for one transfer */
		# define PL08X_LLI_TSFR_SIZE 0x2000

		/* Maximum times we call dma_pool_alloc on this pool without freeing */
		#define PL08X_MAX_ALLOCS 0x40
		#define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
		#define PL08X_ALIGN 8

		@@ -495,10 +491,10 @@ static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,

		struct pl08x_lli_build_data {
		struct pl08x_txd *txd;
		struct pl08x_driver_data *pl08x;
		struct pl08x_bus_data srcbus;
		struct pl08x_bus_data dstbus;
		size_t remainder;
		u32 lli_bus;
		};

		/*
		@@ -551,8 +547,7 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
		llis_va[num_llis].src = bd->srcbus.addr;
		llis_va[num_llis].dst = bd->dstbus.addr;
		llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
		if (bd->pl08x->lli_buses & PL08X_AHB2)
		llis_va[num_llis].lli \|= PL080_LLI_LM_AHB2;
		llis_va[num_llis].lli \|= bd->lli_bus;

		if (cctl & PL080_CONTROL_SRC_INCR)
		bd->srcbus.addr += len;
		@@ -605,9 +600,9 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
		cctl = txd->cctl;

		bd.txd = txd;
		bd.pl08x = pl08x;
		bd.srcbus.addr = txd->src_addr;
		bd.dstbus.addr = txd->dst_addr;
		bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;

		/* Find maximum width of the source bus */
		bd.srcbus.maxwidth =
		@@ -622,25 +617,15 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
		/* Set up the bus widths to the maximum */
		bd.srcbus.buswidth = bd.srcbus.maxwidth;
		bd.dstbus.buswidth = bd.dstbus.maxwidth;
		dev_vdbg(&pl08x->adev->dev,
		"%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
		__func__, bd.srcbus.buswidth, bd.dstbus.buswidth);


		/*
		* Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
		*/
		max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
		PL080_CONTROL_TRANSFER_SIZE_MASK;
		dev_vdbg(&pl08x->adev->dev,
		"%s max bytes per lli = %zu\n",
		__func__, max_bytes_per_lli);

		/* We need to count this down to zero */
		bd.remainder = txd->len;
		dev_vdbg(&pl08x->adev->dev,
		"%s remainder = %zu\n",
		__func__, bd.remainder);

		/*
		* Choose bus to align to
		@@ -649,6 +634,16 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
		*/
		pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);

		dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n",
		bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
		bd.srcbus.buswidth,
		bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
		bd.dstbus.buswidth,
		bd.remainder, max_bytes_per_lli);
		dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
		mbus == &bd.srcbus ? "src" : "dst",
		sbus == &bd.srcbus ? "src" : "dst");

		if (txd->len < mbus->buswidth) {
		/* Less than a bus width available - send as single bytes */
		while (bd.remainder) {
		@@ -840,15 +835,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
		{
		int i;

		dev_vdbg(&pl08x->adev->dev,
		"%-3s %-9s %-10s %-10s %-10s %s\n",
		"lli", "", "csrc", "cdst", "clli", "cctl");
		for (i = 0; i < num_llis; i++) {
		dev_vdbg(&pl08x->adev->dev,
		"lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
		i,
		&llis_va[i],
		llis_va[i].src,
		llis_va[i].dst,
		llis_va[i].cctl,
		llis_va[i].lli
		"%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
		i, &llis_va[i], llis_va[i].src,
		llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
		);
		}
		}
		@@ -1054,64 +1048,105 @@ pl08x_dma_tx_status(struct dma_chan *chan,

		/* PrimeCell DMA extension */
		struct burst_table {
		int burstwords;
		u32 burstwords;
		u32 reg;
		};

		static const struct burst_table burst_sizes[] = {
		{
		.burstwords = 256,
		.reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_256,
		},
		{
		.burstwords = 128,
		.reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_128,
		},
		{
		.burstwords = 64,
		.reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_64,
		},
		{
		.burstwords = 32,
		.reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_32,
		},
		{
		.burstwords = 16,
		.reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_16,
		},
		{
		.burstwords = 8,
		.reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_8,
		},
		{
		.burstwords = 4,
		.reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
		.reg = PL080_BSIZE_4,
		},
		{
		.burstwords = 1,
		.reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
		.burstwords = 0,
		.reg = PL080_BSIZE_1,
		},
		};

		/*
		* Given the source and destination available bus masks, select which
		* will be routed to each port. We try to have source and destination
		* on separate ports, but always respect the allowable settings.
		*/
		static u32 pl08x_select_bus(u8 src, u8 dst)
		{
		u32 cctl = 0;

		if (!(dst & PL08X_AHB1) \|\| ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
		cctl \|= PL080_CONTROL_DST_AHB2;
		if (!(src & PL08X_AHB1) \|\| ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
		cctl \|= PL080_CONTROL_SRC_AHB2;

		return cctl;
		}

		static u32 pl08x_cctl(u32 cctl)
		{
		cctl &= ~(PL080_CONTROL_SRC_AHB2 \| PL080_CONTROL_DST_AHB2 \|
		PL080_CONTROL_SRC_INCR \| PL080_CONTROL_DST_INCR \|
		PL080_CONTROL_PROT_MASK);

		/* Access the cell in privileged mode, non-bufferable, non-cacheable */
		return cctl \| PL080_CONTROL_PROT_SYS;
		}

		static u32 pl08x_width(enum dma_slave_buswidth width)
		{
		switch (width) {
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
		return PL080_WIDTH_8BIT;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
		return PL080_WIDTH_16BIT;
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
		return PL080_WIDTH_32BIT;
		default:
		return ~0;
		}
		}

		static u32 pl08x_burst(u32 maxburst)
		{
		int i;

		for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
		if (burst_sizes[i].burstwords <= maxburst)
		break;

		return burst_sizes[i].reg;
		}

		static int dma_set_runtime_config(struct dma_chan *chan,
		struct dma_slave_config *config)
		{
		struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
		struct pl08x_driver_data *pl08x = plchan->host;
		struct pl08x_channel_data *cd = plchan->cd;
		enum dma_slave_buswidth addr_width;
		dma_addr_t addr;
		u32 maxburst;
		u32 width, burst, maxburst;
		u32 cctl = 0;
		int i;

		if (!plchan->slave)
		return -EINVAL;
		@@ -1119,11 +1154,9 @@ static int dma_set_runtime_config(struct dma_chan *chan,
		/* Transfer direction */
		plchan->runtime_direction = config->direction;
		if (config->direction == DMA_TO_DEVICE) {
		addr = config->dst_addr;
		addr_width = config->dst_addr_width;
		maxburst = config->dst_maxburst;
		} else if (config->direction == DMA_FROM_DEVICE) {
		addr = config->src_addr;
		addr_width = config->src_addr_width;
		maxburst = config->src_maxburst;
		} else {
		@@ -1132,46 +1165,40 @@ static int dma_set_runtime_config(struct dma_chan *chan,
		return -EINVAL;
		}

		switch (addr_width) {
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
		cctl \|= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) \|
		(PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
		break;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
		cctl \|= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) \|
		(PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
		break;
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
		cctl \|= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) \|
		(PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
		break;
		default:
		width = pl08x_width(addr_width);
		if (width == ~0) {
		dev_err(&pl08x->adev->dev,
		"bad runtime_config: alien address width\n");
		return -EINVAL;
		}

		cctl \|= width << PL080_CONTROL_SWIDTH_SHIFT;
		cctl \|= width << PL080_CONTROL_DWIDTH_SHIFT;

		/*
		* Now decide on a maxburst:
		* If this channel will only request single transfers, set this
		* down to ONE element. Also select one element if no maxburst
		* is specified.
		*/
		if (plchan->cd->single \|\| maxburst == 0) {
		cctl \|= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) \|
		(PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
		if (plchan->cd->single)
		maxburst = 1;

		burst = pl08x_burst(maxburst);
		cctl \|= burst << PL080_CONTROL_SB_SIZE_SHIFT;
		cctl \|= burst << PL080_CONTROL_DB_SIZE_SHIFT;

		if (plchan->runtime_direction == DMA_FROM_DEVICE) {
		plchan->src_addr = config->src_addr;
		plchan->src_cctl = pl08x_cctl(cctl) \| PL080_CONTROL_DST_INCR \|
		pl08x_select_bus(plchan->cd->periph_buses,
		pl08x->mem_buses);
		} else {
		for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
		if (burst_sizes[i].burstwords <= maxburst)
		break;
		cctl \|= burst_sizes[i].reg;
		plchan->dst_addr = config->dst_addr;
		plchan->dst_cctl = pl08x_cctl(cctl) \| PL080_CONTROL_SRC_INCR \|
		pl08x_select_bus(pl08x->mem_buses,
		plchan->cd->periph_buses);
		}

		plchan->runtime_addr = addr;

		/* Modify the default channel data to fit PrimeCell request */
		cd->cctl = cctl;

		dev_dbg(&pl08x->adev->dev,
		"configured channel %s (%s) for %s, data width %d, "
		"maxburst %d words, LE, CCTL=0x%08x\n",
		@@ -1270,23 +1297,6 @@ static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
		return 0;
		}

		/*
		* Given the source and destination available bus masks, select which
		* will be routed to each port. We try to have source and destination
		* on separate ports, but always respect the allowable settings.
		*/
		static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
		{
		u32 cctl = 0;

		if (!(dst & PL08X_AHB1) \|\| ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
		cctl \|= PL080_CONTROL_DST_AHB2;
		if (!(src & PL08X_AHB1) \|\| ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
		cctl \|= PL080_CONTROL_SRC_AHB2;

		return cctl;
		}

		static struct pl08x_txd pl08x_get_txd(struct pl08x_dma_chan plchan,
		unsigned long flags)
		{
		@@ -1338,8 +1348,8 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
		txd->cctl \|= PL080_CONTROL_SRC_INCR \| PL080_CONTROL_DST_INCR;

		if (pl08x->vd->dualmaster)
		txd->cctl \|= pl08x_select_bus(pl08x,
		pl08x->mem_buses, pl08x->mem_buses);
		txd->cctl \|= pl08x_select_bus(pl08x->mem_buses,
		pl08x->mem_buses);

		ret = pl08x_prep_channel_resources(plchan, txd);
		if (ret)
		@@ -1356,7 +1366,6 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
		struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
		struct pl08x_driver_data *pl08x = plchan->host;
		struct pl08x_txd *txd;
		u8 src_buses, dst_buses;
		int ret;

		/*
		@@ -1390,42 +1399,22 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
		txd->direction = direction;
		txd->len = sgl->length;

		txd->cctl = plchan->cd->cctl &
		~(PL080_CONTROL_SRC_AHB2 \| PL080_CONTROL_DST_AHB2 \|
		PL080_CONTROL_SRC_INCR \| PL080_CONTROL_DST_INCR \|
		PL080_CONTROL_PROT_MASK);

		/* Access the cell in privileged mode, non-bufferable, non-cacheable */
		txd->cctl \|= PL080_CONTROL_PROT_SYS;

		if (direction == DMA_TO_DEVICE) {
		txd->ccfg \|= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
		txd->cctl \|= PL080_CONTROL_SRC_INCR;
		txd->cctl = plchan->dst_cctl;
		txd->src_addr = sgl->dma_address;
		if (plchan->runtime_addr)
		txd->dst_addr = plchan->runtime_addr;
		else
		txd->dst_addr = plchan->cd->addr;
		src_buses = pl08x->mem_buses;
		dst_buses = plchan->cd->periph_buses;
		txd->dst_addr = plchan->dst_addr;
		} else if (direction == DMA_FROM_DEVICE) {
		txd->ccfg \|= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
		txd->cctl \|= PL080_CONTROL_DST_INCR;
		if (plchan->runtime_addr)
		txd->src_addr = plchan->runtime_addr;
		else
		txd->src_addr = plchan->cd->addr;
		txd->cctl = plchan->src_cctl;
		txd->src_addr = plchan->src_addr;
		txd->dst_addr = sgl->dma_address;
		src_buses = plchan->cd->periph_buses;
		dst_buses = pl08x->mem_buses;
		} else {
		dev_err(&pl08x->adev->dev,
		"%s direction unsupported\n", __func__);
		return NULL;
		}

		txd->cctl \|= pl08x_select_bus(pl08x, src_buses, dst_buses);

		ret = pl08x_prep_channel_resources(plchan, txd);
		if (ret)
		return NULL;
		@@ -1676,6 +1665,20 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
		return mask ? IRQ_HANDLED : IRQ_NONE;
		}

		static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
		{
		u32 cctl = pl08x_cctl(chan->cd->cctl);

		chan->slave = true;
		chan->name = chan->cd->bus_id;
		chan->src_addr = chan->cd->addr;
		chan->dst_addr = chan->cd->addr;
		chan->src_cctl = cctl \| PL080_CONTROL_DST_INCR \|
		pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
		chan->dst_cctl = cctl \| PL080_CONTROL_SRC_INCR \|
		pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
		}

		/*
		* Initialise the DMAC memcpy/slave channels.
		* Make a local wrapper to hold required data
		@@ -1707,9 +1710,8 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
		chan->state = PL08X_CHAN_IDLE;

		if (slave) {
		chan->slave = true;
		chan->name = pl08x->pd->slave_channels[i].bus_id;
		chan->cd = &pl08x->pd->slave_channels[i];
		pl08x_dma_slave_init(chan);
		} else {
		chan->cd = &pl08x->pd->memcpy_channel;
		chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);

drivers/dma/at_hdmac.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1216,7 +1216,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
		atdma->dma_common.cap_mask = pdata->cap_mask;
		atdma->all_chan_mask = (1 << pdata->nr_channels) - 1;

		size = io->end - io->start + 1;
		size = resource_size(io);
		if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
		err = -EBUSY;
		goto err_kfree;
		@@ -1362,7 +1362,7 @@ static int __exit at_dma_remove(struct platform_device *pdev)
		atdma->regs = NULL;

		io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		release_mem_region(io->start, io->end - io->start + 1);
		release_mem_region(io->start, resource_size(io));

		kfree(atdma);

drivers/dma/coh901318.c

+12 −7

Original line number	Diff line number	Diff line
		@@ -41,6 +41,8 @@ struct coh901318_desc {
		struct coh901318_lli *lli;
		enum dma_data_direction dir;
		unsigned long flags;
		u32 head_config;
		u32 head_ctrl;
		};

		struct coh901318_base {
		@@ -661,6 +663,9 @@ static struct coh901318_desc coh901318_queue_start(struct coh901318_chan cohc)

		coh901318_desc_submit(cohc, cohd);

		/* Program the transaction head */
		coh901318_set_conf(cohc, cohd->head_config);
		coh901318_set_ctrl(cohc, cohd->head_ctrl);
		coh901318_prep_linked_list(cohc, cohd->lli);

		/* start dma job on this channel */
		@@ -1091,8 +1096,6 @@ coh901318_prep_slave_sg(struct dma_chan chan, struct scatterlist sgl,
		} else
		goto err_direction;

		coh901318_set_conf(cohc, config);

		/* The dma only supports transmitting packages up to
		* MAX_DMA_PACKET_SIZE. Calculate to total number of
		* dma elemts required to send the entire sg list
		@@ -1129,16 +1132,18 @@ coh901318_prep_slave_sg(struct dma_chan chan, struct scatterlist sgl,
		if (ret)
		goto err_lli_fill;

		/*
		* Set the default ctrl for the channel to the one from the lli,
		* things may have changed due to odd buffer alignment etc.
		*/
		coh901318_set_ctrl(cohc, lli->control);

		COH_DBG(coh901318_list_print(cohc, lli));

		/* Pick a descriptor to handle this transfer */
		cohd = coh901318_desc_get(cohc);
		cohd->head_config = config;
		/*
		* Set the default head ctrl for the channel to the one from the
		* lli, things may have changed due to odd buffer alignment
		* etc.
		*/
		cohd->head_ctrl = lli->control;
		cohd->dir = direction;
		cohd->flags = flags;
		cohd->desc.tx_submit = coh901318_tx_submit;