Loading arch/arm/kernel/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -84,6 +84,7 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o CFLAGS_pj4-cp0.o := -marm AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o Loading arch/arm/kernel/iwmmxt.S +13 −0 Original line number Diff line number Diff line Loading @@ -58,6 +58,7 @@ #define MMX_SIZE (0x98) .text .arm /* * Lazy switching of Concan coprocessor context Loading Loading @@ -182,6 +183,8 @@ concan_load: tmcr wCon, r2 ret lr ENDPROC(iwmmxt_task_enable) /* * Back up Concan regs to save area and disable access to them * (mainly for gdb or sleep mode usage) Loading Loading @@ -232,6 +235,8 @@ ENTRY(iwmmxt_task_disable) 1: msr cpsr_c, ip @ restore interrupt mode ldmfd sp!, {r4, pc} ENDPROC(iwmmxt_task_disable) /* * Copy Concan state to given memory address * Loading Loading @@ -268,6 +273,8 @@ ENTRY(iwmmxt_task_copy) msr cpsr_c, ip @ restore interrupt mode ret r3 ENDPROC(iwmmxt_task_copy) /* * Restore Concan state from given memory address * Loading Loading @@ -304,6 +311,8 @@ ENTRY(iwmmxt_task_restore) msr cpsr_c, ip @ restore interrupt mode ret r3 ENDPROC(iwmmxt_task_restore) /* * Concan handling on task switch * Loading Loading @@ -335,6 +344,8 @@ ENTRY(iwmmxt_task_switch) mrc p15, 0, r1, c2, c0, 0 sub pc, lr, r1, lsr #32 @ cpwait and return ENDPROC(iwmmxt_task_switch) /* * Remove Concan ownership of given task * Loading @@ -353,6 +364,8 @@ ENTRY(iwmmxt_task_release) msr cpsr_c, r2 @ restore interrupts ret lr ENDPROC(iwmmxt_task_release) .data concan_owner: .word 0 Loading Loading
arch/arm/kernel/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -84,6 +84,7 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o CFLAGS_pj4-cp0.o := -marm AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o Loading
arch/arm/kernel/iwmmxt.S +13 −0 Original line number Diff line number Diff line Loading @@ -58,6 +58,7 @@ #define MMX_SIZE (0x98) .text .arm /* * Lazy switching of Concan coprocessor context Loading Loading @@ -182,6 +183,8 @@ concan_load: tmcr wCon, r2 ret lr ENDPROC(iwmmxt_task_enable) /* * Back up Concan regs to save area and disable access to them * (mainly for gdb or sleep mode usage) Loading Loading @@ -232,6 +235,8 @@ ENTRY(iwmmxt_task_disable) 1: msr cpsr_c, ip @ restore interrupt mode ldmfd sp!, {r4, pc} ENDPROC(iwmmxt_task_disable) /* * Copy Concan state to given memory address * Loading Loading @@ -268,6 +273,8 @@ ENTRY(iwmmxt_task_copy) msr cpsr_c, ip @ restore interrupt mode ret r3 ENDPROC(iwmmxt_task_copy) /* * Restore Concan state from given memory address * Loading Loading @@ -304,6 +311,8 @@ ENTRY(iwmmxt_task_restore) msr cpsr_c, ip @ restore interrupt mode ret r3 ENDPROC(iwmmxt_task_restore) /* * Concan handling on task switch * Loading Loading @@ -335,6 +344,8 @@ ENTRY(iwmmxt_task_switch) mrc p15, 0, r1, c2, c0, 0 sub pc, lr, r1, lsr #32 @ cpwait and return ENDPROC(iwmmxt_task_switch) /* * Remove Concan ownership of given task * Loading @@ -353,6 +364,8 @@ ENTRY(iwmmxt_task_release) msr cpsr_c, r2 @ restore interrupts ret lr ENDPROC(iwmmxt_task_release) .data concan_owner: .word 0 Loading