Merge branch 'samsung/board' into next/board (127d4eb9) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/mach-exynos4/Kconfig

+14 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,11 @@ config SOC_EXYNOS4212
		help
		Enable EXYNOS4212 SoC support

		config SOC_EXYNOS4412
		bool
		help
		Enable EXYNOS4412 SoC support

		config EXYNOS4_MCT
		bool
		default y
		@@ -243,6 +248,15 @@ config MACH_SMDK4212
		help
		Machine support for Samsung SMDK4212

		comment "EXYNOS4412 Boards"

		config MACH_SMDK4412
		bool "SMDK4412"
		select SOC_EXYNOS4412
		select MACH_SMDK4212
		help
		Machine support for Samsung SMDK4412

		endmenu

		comment "Configuration for HSMMC bus width"

arch/arm/mach-exynos4/Makefile

+2 −1

Original line number	Diff line number	Diff line
		@@ -34,7 +34,8 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
		obj-$(CONFIG_MACH_NURI) += mach-nuri.o
		obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o

		obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o
		obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
		obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o

		# device support

arch/arm/mach-exynos4/clock.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1149,7 +1149,7 @@ static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
		if (soc_is_exynos4210())
		return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
		pll_4508);
		else if (soc_is_exynos4212())
		else if (soc_is_exynos4212() \|\| soc_is_exynos4412())
		return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
		else
		return 0;
		@@ -1200,7 +1200,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
		vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
		__raw_readl(S5P_VPLL_CON1), pll_4650c);
		} else if (soc_is_exynos4212()) {
		} else if (soc_is_exynos4212() \|\| soc_is_exynos4412()) {
		apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
		mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
		epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),

arch/arm/mach-exynos4/cpu.c

+15 −6

Original line number	Diff line number	Diff line
		@@ -32,6 +32,8 @@
		#include <mach/regs-irq.h>
		#include <mach/regs-pmu.h>

		unsigned int gic_bank_offset __read_mostly;

		extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
		unsigned int irq_start);
		extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
		@@ -191,27 +193,34 @@ void __init exynos4_init_clocks(int xtal)

		if (soc_is_exynos4210())
		exynos4210_register_clocks();
		else if (soc_is_exynos4212())
		else if (soc_is_exynos4212() \|\| soc_is_exynos4412())
		exynos4212_register_clocks();

		exynos4_register_clocks();
		exynos4_setup_clocks();
		}

		static void exynos4_gic_irq_eoi(struct irq_data *d)
		static void exynos4_gic_irq_fix_base(struct irq_data *d)
		{
		struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);

		gic_data->cpu_base = S5P_VA_GIC_CPU +
		(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
		(gic_bank_offset * smp_processor_id());

		gic_data->dist_base = S5P_VA_GIC_DIST +
		(gic_bank_offset * smp_processor_id());
		}

		void __init exynos4_init_irq(void)
		{
		int irq;

		gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
		gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
		gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

		gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
		gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
		gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
		gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;

		for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

		@@ -250,7 +259,7 @@ static int __init exynos4_l2x0_cache_init(void)

		if (soc_is_exynos4210())
		__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
		else if (soc_is_exynos4212())
		else if (soc_is_exynos4212() \|\| soc_is_exynos4412())
		__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);

		/* L2X0 Prefetch Control */

arch/arm/mach-exynos4/include/mach/entry-macro.S

+24 −5

Original line number	Diff line number	Diff line
		@@ -17,12 +17,25 @@
		.endm

		.macro get_irqnr_preamble, base, tmp
		ldr \base, =gic_cpu_base_addr
		mov \tmp, #0

		mrc p15, 0, \base, c0, c0, 5
		and \base, \base, #3
		cmp \base, #0
		beq 1f

		ldr \tmp, =gic_bank_offset
		ldr \tmp, [\tmp]
		cmp \base, #1
		beq 1f

		cmp \base, #2
		addeq \tmp, \tmp, \tmp
		addne \tmp, \tmp, \tmp, LSL #1

		1: ldr \base, =gic_cpu_base_addr
		ldr \base, [\base]
		mrc p15, 0, \tmp, c0, c0, 5
		and \tmp, \tmp, #3
		cmp \tmp, #1
		addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
		add \base, \base, \tmp
		.endm

		.macro arch_ret_to_user, tmp1, tmp2
		@@ -80,4 +93,10 @@
		/* As above, this assumes that irqstat and base are preserved.. */

		.macro test_for_ltirq, irqnr, irqstat, base, tmp
		bic \irqnr, \irqstat, #0x1c00
		mov \tmp, #0
		cmp \irqnr, #28
		moveq \tmp, #1
		streq \irqstat, [\base, #GIC_CPU_EOI]
		cmp \tmp, #0
		.endm