ppc440spe-adma: adds updated ppc440spe adma driver (12458ea0) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt

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		PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)

		Device nodes needed for operation of the ppc440spe-adma driver
		are specified hereby. These are I2O/DMA, DMA and XOR nodes
		for DMA engines and Memory Queue Module node. The latter is used
		by ADMA driver for configuration of RAID-6 H/W capabilities of
		the PPC440SPe. In addition to the nodes and properties described
		below, the ranges property of PLB node must specify ranges for
		DMA devices.

		i) The I2O node

		Required properties:

		- compatible : "ibm,i2o-440spe";
		- reg : <registers mapping>
		- dcr-reg : <DCR registers range>

		Example:

		I2O: i2o@400100000 {
		compatible = "ibm,i2o-440spe";
		reg = <0x00000004 0x00100000 0x100>;
		dcr-reg = <0x060 0x020>;
		};


		ii) The DMA node

		Required properties:

		- compatible : "ibm,dma-440spe";
		- cell-index : 1 cell, hardware index of the DMA engine
		(typically 0x0 and 0x1 for DMA0 and DMA1)
		- reg : <registers mapping>
		- dcr-reg : <DCR registers range>
		- interrupts : <interrupt mapping for DMA0/1 interrupts sources:
		2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
		and DMA Error IRQ (on UIC1). The latter is common
		for both DMA engines>.
		- interrupt-parent : needed for interrupt mapping

		Example:

		DMA0: dma0@400100100 {
		compatible = "ibm,dma-440spe";
		cell-index = <0>;
		reg = <0x00000004 0x00100100 0x100>;
		dcr-reg = <0x060 0x020>;
		interrupt-parent = <&DMA0>;
		interrupts = <0 1>;
		#interrupt-cells = <1>;
		#address-cells = <0>;
		#size-cells = <0>;
		interrupt-map = <
		0 &UIC0 0x14 4
		1 &UIC1 0x16 4>;
		};


		iii) XOR Accelerator node

		Required properties:

		- compatible : "amcc,xor-accelerator";
		- reg : <registers mapping>
		- interrupts : <interrupt mapping for XOR interrupt source>
		- interrupt-parent : for interrupt mapping

		Example:

		xor-accel@400200000 {
		compatible = "amcc,xor-accelerator";
		reg = <0x00000004 0x00200000 0x400>;
		interrupt-parent = <&UIC1>;
		interrupts = <0x1f 4>;
		};


		iv) Memory Queue Module node

		Required properties:

		- compatible : "ibm,mq-440spe";
		- dcr-reg : <DCR registers range>

		Example:

		MQ0: mq {
		compatible = "ibm,mq-440spe";
		dcr-reg = <0x040 0x020>;
		};

arch/powerpc/include/asm/async_tx.h

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		/*
		* Copyright (C) 2008-2009 DENX Software Engineering.
		*
		* Author: Yuri Tikhonov <yur@emcraft.com>
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the Free
		* Software Foundation; either version 2 of the License, or (at your option)
		* any later version.
		*
		* This program is distributed in the hope that it will be useful, but WITHOUT
		* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
		* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
		* more details.
		*
		* You should have received a copy of the GNU General Public License along with
		* this program; if not, write to the Free Software Foundation, Inc., 59
		* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
		*
		* The full GNU General Public License is included in this distribution in the
		* file called COPYING.
		*/
		#ifndef _ASM_POWERPC_ASYNC_TX_H_
		#define _ASM_POWERPC_ASYNC_TX_H_

		#if defined(CONFIG_440SPe) \|\| defined(CONFIG_440SP)
		extern struct dma_chan *
		ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap,
		struct page dst_lst, int dst_cnt, struct page src_lst,
		int src_cnt, size_t src_sz);

		#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \
		src_cnt, src_sz) \
		ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \
		src_cnt, src_sz)
		#else

		#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
		__async_tx_find_channel(dep, type)

		struct dma_chan *
		__async_tx_find_channel(struct async_submit_ctl *submit,
		enum dma_transaction_type tx_type);

		#endif

		#endif

arch/powerpc/include/asm/dcr-regs.h

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		@@ -157,4 +157,27 @@
		#define L2C_SNP_SSR_32G 0x0000f000
		#define L2C_SNP_ESR 0x00000800

		/*
		* DCR register offsets for 440SP/440SPe I2O/DMA controller.
		* The base address is configured in the device tree.
		*/
		#define DCRN_I2O0_IBAL 0x006
		#define DCRN_I2O0_IBAH 0x007
		#define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */

		/* 440SP/440SPe Software Reset DCR */
		#define DCRN_SDR0_SRST 0x0200
		#define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */

		/* 440SP/440SPe Memory Queue DCR offsets */
		#define DCRN_MQ0_XORBA 0x04
		#define DCRN_MQ0_CF2H 0x06
		#define DCRN_MQ0_CFBHL 0x0f
		#define DCRN_MQ0_BAUH 0x10

		/* HB/LL Paths Configuration Register */
		#define MQ0_CFBHL_TPLM 28
		#define MQ0_CFBHL_HBCL 23
		#define MQ0_CFBHL_POLY 15

		#endif /* __DCR_REGS_H__ */

drivers/dma/Kconfig

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		@@ -116,6 +116,17 @@ config COH901318
		help
		Enable support for ST-Ericsson COH 901 318 DMA.

		config AMCC_PPC440SPE_ADMA
		tristate "AMCC PPC440SPe ADMA support"
		depends on 440SPe \|\| 440SP
		select DMA_ENGINE
		select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
		help
		Enable support for the AMCC PPC440SPe RAID engines.

		config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
		bool

		config DMA_ENGINE
		bool

drivers/dma/Makefile

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		@@ -11,3 +11,4 @@ obj-$(CONFIG_MX3_IPU) += ipu/
		obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
		obj-$(CONFIG_SH_DMAE) += shdma.o
		obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
		obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/