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Commit 11ef3f1f authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add some missing semaphore init 



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 44517c44

drivers/gpu/drm/radeon/evergreen.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1455,6 +1455,7 @@ int evergreen_cp_resume(struct radeon_device *rdev) 
#endif

#endif

	WREG32(CP_RB_CNTL, tmp);

	WREG32(CP_RB_CNTL, tmp);

	WREG32(CP_SEM_WAIT_TIMER, 0x0);

	WREG32(CP_SEM_WAIT_TIMER, 0x0);

	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);





	/* Set the write pointer delay */

	/* Set the write pointer delay */

	WREG32(CP_RB_WPTR_DELAY, 0);

	WREG32(CP_RB_WPTR_DELAY, 0);

drivers/gpu/drm/radeon/evergreend.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -108,6 +108,7 @@ 
#define	CP_RB_WPTR_ADDR_HI				0xC11C

#define	CP_RB_WPTR_ADDR_HI				0xC11C

#define	CP_RB_WPTR_DELAY				0x8704

#define	CP_RB_WPTR_DELAY				0x8704

#define	CP_SEM_WAIT_TIMER				0x85BC

#define	CP_SEM_WAIT_TIMER				0x85BC

#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8

#define	CP_DEBUG					0xC1FC

#define	CP_DEBUG					0xC1FC

drivers/gpu/drm/radeon/ni.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1219,6 +1219,7 @@ int cayman_cp_resume(struct radeon_device *rdev) 
	RREG32(GRBM_SOFT_RESET);

	RREG32(GRBM_SOFT_RESET);





	WREG32(CP_SEM_WAIT_TIMER, 0x0);

	WREG32(CP_SEM_WAIT_TIMER, 0x0);

	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);





	/* Set the write pointer delay */

	/* Set the write pointer delay */

	WREG32(CP_RB_WPTR_DELAY, 0);

	WREG32(CP_RB_WPTR_DELAY, 0);

drivers/gpu/drm/radeon/nid.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -222,6 +222,7 @@ 
#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_ADDR					0x8544

#define	SCRATCH_ADDR					0x8544

#define	CP_SEM_WAIT_TIMER				0x85BC

#define	CP_SEM_WAIT_TIMER				0x85BC

#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8

#define	CP_COHER_CNTL2					0x85E8

#define	CP_COHER_CNTL2					0x85E8

#define CP_ME_CNTL					0x86D8

#define CP_ME_CNTL					0x86D8

#define		CP_ME_HALT					(1 << 28)

#define		CP_ME_HALT					(1 << 28)