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Commit 11116601 authored by Douglas Thompson's avatar Douglas Thompson Committed by Linus Torvalds
Browse files

drivers/edac: Lindent i82443bxgx 



Run i82443bxgx.c file through Lindent for cleanup

Signed-off-by: default avatarDouglas Thompson <dougthompson@xmission.com>
Signed-off-by: default avatarDave Jiang <djiang@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 203333cb

drivers/edac/i82443bxgx_edac.c

+72 −88
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 


#define EDAC_MOD_STR    "i82443bxgx_edac"





/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory

 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory

 * rows" "The 82443BX supports multiple-bit error detection and
@@ -61,8 +60,6 @@ 
#define I82443BXGX_NR_CHANS  1

#define I82443BXGX_NR_DIMMS  4







/* 82443 PCI Device 0 */

#define I82443BXGX_NBXCFG 0x50	/* 32bit register starting at this PCI

				 * config space offset */
@@ -78,7 +75,6 @@ 


#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE  6





/* 82443 PCI Device 0 */

#define I82443BXGX_EAP   0x80	/* 32bit register starting at this PCI

				 * config space offset, Error Address
@@ -99,7 +95,6 @@ 
#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1	/* 3 bits - first err row singlebit */

#define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0)	/* 1 = SBE occurred */





#define I82443BXGX_DRAMC 0x57	/* 8bit register starting at this PCI

				 * config space offset. */

#define I82443BXGX_DRAMC_OFFSET_DT 3	/* 2 bits, DRAM Type */
@@ -107,21 +102,18 @@ 
#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1	/* 01 = SDRAM */

#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2	/* 10 = Registered SDRAM */





#define I82443BXGX_DRB 0x60	/* 8x 8bit registers starting at this PCI

				 * config space offset. */





/* FIXME - don't poll when ECC disabled? */





struct i82443bxgx_edacmc_error_info {

	u32 eap;

};





static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,

		struct i82443bxgx_edacmc_error_info *info)

					     struct i82443bxgx_edacmc_error_info

					     *info)

{

	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);
@@ -139,9 +131,10 @@ static void i82443bxgx_edacmc_get_error_info (struct mem_ctl_info *mci, 
				 I82443BXGX_EAP_OFFSET_MBE);

}





static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,

		struct i82443bxgx_edacmc_error_info *info, int handle_errors)

						struct

						i82443bxgx_edacmc_error_info

						*info, int handle_errors)

{

	int error_found = 0;

	u32 eapaddr, page, pageoffset;
@@ -155,20 +148,16 @@ static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci, 
	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {

		error_found = 1;

		if (handle_errors)

			edac_mc_handle_ce(

				mci, page, pageoffset,

			edac_mc_handle_ce(mci, page, pageoffset,

					  /* 440BX/GX don't make syndrome information available */

				0,

				edac_mc_find_csrow_by_page(mci, page),

				0,	/* channel */

					  0, edac_mc_find_csrow_by_page(mci, page), 0,	/* channel */

					  mci->ctl_name);

	}



	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {

		error_found = 1;

		if (handle_errors)

			edac_mc_handle_ue(

				mci, page, pageoffset,

			edac_mc_handle_ue(mci, page, pageoffset,

					  edac_mc_find_csrow_by_page(mci, page),

					  mci->ctl_name);

	}
@@ -176,7 +165,6 @@ static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci, 
	return error_found;

}





static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)

{

	struct i82443bxgx_edacmc_error_info info;
@@ -186,7 +174,6 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) 
	i82443bxgx_edacmc_process_error_info(mci, &info, 1);

}





static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,

				   struct pci_dev *pdev,

				   enum edac_type edac_mode,
@@ -233,7 +220,6 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, 
	}

}





static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)

{

	struct mem_ctl_info *mci;
@@ -270,7 +256,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) 
		mtype = MEM_RDR;

		break;

	default:

		debugf0("Unknown/reserved DRAM type value in DRAMC register!\n");

		debugf0

		    ("Unknown/reserved DRAM type value in DRAMC register!\n");

		mtype = -MEM_UNKNOWN;

	}
@@ -285,8 +272,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) 
		    (BIT(0) | BIT(1)));



	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)

		? SCRUB_HW_SRC

		: SCRUB_NONE;

	    ? SCRUB_HW_SRC : SCRUB_NONE;



	switch (ecc_mode) {

	case I82443BXGX_NBXCFG_INTEGRITY_NONE:
@@ -300,7 +286,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) 
		edac_mode = EDAC_SECDED;

		break;

	default:

		debugf0("%s(): Unknown/reserved ECC state in NBXCFG register!\n",

		debugf0

		    ("%s(): Unknown/reserved ECC state in NBXCFG register!\n",

		     __func__);

		edac_mode = EDAC_UNKNOWN;

		break;
@@ -312,8 +299,10 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) 
	 * here, or we get "phantom" errors occuring at module-load

	 * time. */

	pci_write_bits32(pdev, I82443BXGX_EAP,

			 (I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE),

			 (I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE));

			 (I82443BXGX_EAP_OFFSET_SBE |

			  I82443BXGX_EAP_OFFSET_MBE),

			 (I82443BXGX_EAP_OFFSET_SBE |

			  I82443BXGX_EAP_OFFSET_MBE));



	mci->mod_name = EDAC_MOD_STR;

	mci->mod_ver = I82443_REVISION;
@@ -334,6 +323,7 @@ fail: 
	edac_mc_free(mci);

	return -ENODEV;

}



EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);



/* returns count (>= 0), or negative on error */
@@ -346,7 +336,6 @@ static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, 
	return i82443bxgx_edacmc_probe1(pdev, ent->driver_data);

}





static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)

{

	struct mem_ctl_info *mci;
@@ -358,8 +347,8 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) 


	edac_mc_free(mci);

}

EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);



EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);



static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {

	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
@@ -371,7 +360,6 @@ static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = { 


MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);





static struct pci_driver i82443bxgx_edacmc_driver = {

	.name = EDAC_MOD_STR,

	.probe = i82443bxgx_edacmc_init_one,
@@ -379,23 +367,19 @@ static struct pci_driver i82443bxgx_edacmc_driver = { 
	.id_table = i82443bxgx_pci_tbl,

};





static int __init i82443bxgx_edacmc_init(void)

{

	return pci_register_driver(&i82443bxgx_edacmc_driver);

}





static void __exit i82443bxgx_edacmc_exit(void)

{

	pci_unregister_driver(&i82443bxgx_edacmc_driver);

}





module_init(i82443bxgx_edacmc_init);

module_exit(i82443bxgx_edacmc_exit);





MODULE_LICENSE("GPL");

MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");

MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");