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Commit 1051125d authored by Vipul Pandya's avatar Vipul Pandya Committed by David S. Miller
Browse files

net: sxgbe: add TSO support for Samsung sxgbe



Enable TSO during initialization for each DMA channels

Signed-off-by: default avatarVipul Pandya <vipul.pandya@samsung.com>
Neatening-by: default avatarJoe Perches <joe@perches.com>
Signed-off-by: default avatarByungho An <bh74.an@samsung.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent acc18c14
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+1 −0
Original line number Diff line number Diff line
@@ -371,6 +371,7 @@ struct sxgbe_tx_queue {
	u32 tx_coal_frames;
	u32 tx_coal_timer;
	int hwts_tx_en;
	u16 prev_mss;
	u8 queue_no;
};

+1 −1
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ static int sxgbe_tx_ctxt_desc_get_owner(struct sxgbe_tx_ctxt_desc *p)
}

/* Set TX mss in TX context Descriptor */
static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, int mss)
static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, u16 mss)
{
	p->maxseg_size = mss;
}
+2 −2
Original line number Diff line number Diff line
@@ -168,7 +168,7 @@ struct sxgbe_desc_ops {

	/* Invoked by the xmit function to prepare the tx descriptor */
	void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse,
				   u32 total_hdr_len, u32 payload_len,
				   u32 total_hdr_len, u32 tcp_hdr_len,
				   u32 tcp_payload_len);

	/* Assign buffer lengths for descriptor */
@@ -217,7 +217,7 @@ struct sxgbe_desc_ops {
	int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p);

	/* Set TX mss */
	void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, int mss);
	void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss);

	/* Set TX mss */
	int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p);
+10 −0
Original line number Diff line number Diff line
@@ -349,6 +349,15 @@ static void sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt)
	}
}

static void sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num)
{
	u32 ctrl;

	ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));
	ctrl |= SXGBE_DMA_CHA_TXCTL_TSE_ENABLE;
	writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));
}

static const struct sxgbe_dma_ops sxgbe_dma_ops = {
	.init				= sxgbe_dma_init,
	.cha_init			= sxgbe_dma_channel_init,
@@ -364,6 +373,7 @@ static const struct sxgbe_dma_ops sxgbe_dma_ops = {
	.tx_dma_int_status		= sxgbe_tx_dma_int_status,
	.rx_dma_int_status		= sxgbe_rx_dma_int_status,
	.rx_watchdog			= sxgbe_dma_rx_watchdog,
	.enable_tso			= sxgbe_enable_tso,
};

const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void)
+2 −0
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ struct sxgbe_dma_ops {
				 struct sxgbe_extra_stats *x);
	/* Program the HW RX Watchdog */
	void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt);
	/* Enable TSO for each DMA channel */
	void (*enable_tso)(void __iomem *ioaddr, u8 chan_num);
};

const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void);
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