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Commit 0fe422c9 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'omap/omap1' into next/devel

parents 5611cc45 c116abc4

arch/arm/configs/omap1_defconfig

+0 −6
Original line number Diff line number Diff line
@@ -48,12 +48,6 @@ CONFIG_MACH_SX1=y 
CONFIG_MACH_NOKIA770=y

CONFIG_MACH_AMS_DELTA=y

CONFIG_MACH_OMAP_GENERIC=y

CONFIG_OMAP_ARM_216MHZ=y

CONFIG_OMAP_ARM_195MHZ=y

CONFIG_OMAP_ARM_192MHZ=y

CONFIG_OMAP_ARM_182MHZ=y

CONFIG_OMAP_ARM_168MHZ=y

# CONFIG_OMAP_ARM_60MHZ is not set

# CONFIG_ARM_THUMB is not set

CONFIG_PCCARD=y

CONFIG_OMAP_CF=y

arch/arm/mach-omap1/Kconfig

+0 −64
Original line number Diff line number Diff line
@@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC 
          custom OMAP boards. Say Y here if you have a custom

          board.



comment "OMAP CPU Speed"

	depends on ARCH_OMAP1



config OMAP_ARM_216MHZ

	bool "OMAP ARM 216 MHz CPU (1710 only)"

        depends on ARCH_OMAP1 && ARCH_OMAP16XX

        help

          Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.



config OMAP_ARM_195MHZ

	bool "OMAP ARM 195 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)

	help

          Enable 195MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_192MHZ

	bool "OMAP ARM 192 MHz CPU"

	depends on ARCH_OMAP1 && ARCH_OMAP16XX

	help

          Enable 192MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_182MHZ

	bool "OMAP ARM 182 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)

	help

          Enable 182MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_168MHZ

	bool "OMAP ARM 168 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)

	help

          Enable 168MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_150MHZ

	bool "OMAP ARM 150 MHz CPU"

	depends on ARCH_OMAP1 && ARCH_OMAP15XX

	help

	  Enable 150MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_120MHZ

	bool "OMAP ARM 120 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)

	help

          Enable 120MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_96MHZ

	bool "OMAP ARM 96 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)

	help

          Enable 96MHz clock for OMAP CPU. If unsure, say N.



config OMAP_ARM_60MHZ

	bool "OMAP ARM 60 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)

        default y

	help

          Enable 60MHz clock for OMAP CPU. If unsure, say Y.



config OMAP_ARM_30MHZ

	bool "OMAP ARM 30 MHz CPU"

	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)

	help

          Enable 30MHz clock for OMAP CPU. If unsure, say N.



endmenu



endif

arch/arm/mach-omap1/clock.c

+6 −8
Original line number Diff line number Diff line
@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) 
	ref_rate = ck_ref_p->rate;



	for (ptr = omap1_rate_table; ptr->rate; ptr++) {

		if (ptr->xtal != ref_rate)

		if (!(ptr->flags & cpu_mask))

			continue;



		/* DPLL1 cannot be reprogrammed without risking system crash */

		if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)

		if (ptr->xtal != ref_rate)

			continue;



		/* Can check only after xtal frequency check */
@@ -215,11 +214,7 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) 
	/*

	 * In most cases we should not need to reprogram DPLL.

	 * Reprogramming the DPLL is tricky, it must be done from SRAM.

	 * (on 730, bit 13 must always be 1)

	 */

	if (cpu_is_omap7xx())

		omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);

	else

	omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);



	/* XXX Do we need to recalculate the tree below DPLL1 at this point? */
@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) 
	highest_rate = -EINVAL;



	for (ptr = omap1_rate_table; ptr->rate; ptr++) {

		if (!(ptr->flags & cpu_mask))

			continue;



		if (ptr->xtal != ref_rate)

			continue;

arch/arm/mach-omap1/clock.h

+3 −0
Original line number Diff line number Diff line
@@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy; 
extern const struct clkops clkops_uart_16xx;

extern const struct clkops clkops_generic;



/* used for passing SoC type to omap1_{select,round_to}_table_rate() */

extern u32 cpu_mask;



#endif

arch/arm/mach-omap1/clock_data.c

+14 −5
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 


#include <linux/kernel.h>

#include <linux/clk.h>

#include <linux/cpufreq.h>

#include <linux/delay.h>

#include <linux/io.h>



#include <asm/mach-types.h>  /* for machine_is_* */
@@ -23,6 +25,7 @@ 
#include <plat/clock.h>

#include <plat/cpu.h>

#include <plat/clkdev_omap.h>

#include <plat/sram.h>	/* for omap_sram_reprogram_clock() */

#include <plat/usb.h>   /* for OTG_BASE */



#include "clock.h"
@@ -776,12 +779,14 @@ static void __init omap1_show_rates(void) 
		arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);

}



u32 cpu_mask;



int __init omap1_clk_init(void)

{

	struct omap_clk *c;

	const struct omap_clock_config *info;

	int crystal_type = 0; /* Default 12 MHz */

	u32 reg, cpu_mask;

	u32 reg;



#ifdef CONFIG_DEBUG_LL

	/*
@@ -806,6 +811,8 @@ int __init omap1_clk_init(void) 
		clk_preinit(c->lk.clk);



	cpu_mask = 0;

	if (cpu_is_omap1710())

		cpu_mask |= CK_1710;

	if (cpu_is_omap16xx())

		cpu_mask |= CK_16XX;

	if (cpu_is_omap1510())
@@ -927,16 +934,18 @@ int __init omap1_clk_init(void) 


void __init omap1_clk_late_init(void)

{

	if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE)

		return;

	unsigned long rate = ck_dpll1.rate;



	/* Find the highest supported frequency and enable it */

	if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {

		pr_err("System frequencies not set, using default. Check your config.\n");

		omap_writew(0x2290, DPLL_CTL);

		omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);

		/*

		 * Reprogramming the DPLL is tricky, it must be done from SRAM.

		 */

		omap_sram_reprogram_clock(0x2290, 0x0005);

		ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;

	}

	propagate_rate(&ck_dpll1);

	omap1_show_rates();

	loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);

}