Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0fc932b8 authored by Jesse Barnes's avatar Jesse Barnes Committed by Chris Wilson
Browse files

drm/i915: factor out FDI disable and add FDI assertions 



Factor out the FDI disable function (make it a mirror of
ironlake_fdi_enable) and add some FDI related assertions to the FDI
training code (we need an active pipe & plane before we start
transmitting bits).

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 040484af

drivers/gpu/drm/i915/intel_display.c

+60 −44
Original line number Diff line number Diff line
@@ -2237,8 +2237,13 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	int plane = intel_crtc->plane;

	u32 reg, temp, tries;



	/* FDI needs bits from pipe & plane first */

	assert_pipe_enabled(dev_priv, pipe);

	assert_plane_enabled(dev_priv, plane);



	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

	   for train result */

	reg = FDI_RX_IMR(pipe);
@@ -2487,6 +2492,60 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc) 
	}

}



static void ironlake_fdi_disable(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	u32 reg, temp;



	/* disable CPU FDI tx and PCH FDI rx */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);

	POSTING_READ(reg);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(0x7 << 16);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);



	POSTING_READ(reg);

	udelay(100);



	/* Ironlake workaround, disable clock pointer after downing FDI */

	if (HAS_PCH_IBX(dev))

		I915_WRITE(FDI_RX_CHICKEN(pipe),

			   I915_READ(FDI_RX_CHICKEN(pipe) &

				     ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));



	/* still set train pattern 1 */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	I915_WRITE(reg, temp);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	if (HAS_PCH_CPT(dev)) {

		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

	} else {

		temp &= ~FDI_LINK_TRAIN_NONE;

		temp |= FDI_LINK_TRAIN_PATTERN_1;

	}

	/* BPC in FDI rx is consistent with that in PIPECONF */

	temp &= ~(0x07 << 16);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	I915_WRITE(reg, temp);



	POSTING_READ(reg);

	udelay(100);

}



/*

 * When we disable a pipe, we need to clear any pending scanline wait events

 * to avoid hanging the ring, which we assume we are waiting on.
@@ -2691,50 +2750,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 
	I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);

	I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);



	/* disable CPU FDI tx and PCH FDI rx */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);

	POSTING_READ(reg);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(0x7 << 16);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);



	POSTING_READ(reg);

	udelay(100);



	/* Ironlake workaround, disable clock pointer after downing FDI */

	if (HAS_PCH_IBX(dev))

		I915_WRITE(FDI_RX_CHICKEN(pipe),

			   I915_READ(FDI_RX_CHICKEN(pipe) &

				     ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));



	/* still set train pattern 1 */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	I915_WRITE(reg, temp);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	if (HAS_PCH_CPT(dev)) {

		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

	} else {

		temp &= ~FDI_LINK_TRAIN_NONE;

		temp |= FDI_LINK_TRAIN_PATTERN_1;

	}

	/* BPC in FDI rx is consistent with that in PIPECONF */

	temp &= ~(0x07 << 16);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	I915_WRITE(reg, temp);



	POSTING_READ(reg);

	udelay(100);

	ironlake_fdi_disable(crtc);



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

		temp = I915_READ(PCH_LVDS);