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Commit 0f846f81 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: disable RCBP and VDS unit clock gating on SNB and VLV 

The RCBP workaround still applies on these chips, and we need VDS as well.

v2: remove MB boot fetch that snuck in (Daniel)
    add workaround tags to comments for easier internal tracking (Daniel)
v3: only apply RCPB and VDS on SNB and VLV, IVB doesn't need them (Eugeni)

References: https://bugs.freedesktop.org/show_bug.cgi?id=50251


Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e080b915

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -4037,6 +4037,7 @@ 
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)

# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)





#define GEN6_UCGCTL2				0x9404

#define GEN6_UCGCTL2				0x9404

# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)

# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)

drivers/gpu/drm/i915/intel_pm.c

+44 −10
Original line number Original line Diff line number Diff line
@@ -3330,8 +3330,12 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
	 *

	 *

	 * According to the spec, bit 11 (RCCUNIT) must also be set,

	 * According to the spec, bit 11 (RCCUNIT) must also be set,

	 * but we didn't debug actual testcases to find it out.

	 * but we didn't debug actual testcases to find it out.

	 *

	 * Also apply WaDisableVDSUnitClockGating and

	 * WaDisableRCPBUnitClockGating.

	 */

	 */

	I915_WRITE(GEN6_UCGCTL2,

	I915_WRITE(GEN6_UCGCTL2,

		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);

		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
@@ -3392,11 +3396,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);





	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 */

	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);

	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);





	I915_WRITE(IVB_CHICKEN3,

	I915_WRITE(IVB_CHICKEN3,
@@ -3413,6 +3412,23 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

			GEN7_WA_L3_CHICKEN_MODE);

			GEN7_WA_L3_CHICKEN_MODE);





	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

	 * gating disable must be set.  Failure to set it results in

	 * flickering pixels due to Z write ordering failures after

	 * some amount of runtime in the Mesa "fire" demo, and Unigine

	 * Sanctuary and Tropics, and apparently anything else with

	 * alpha test or pixel discard.

	 *

	 * According to the spec, bit 11 (RCCUNIT) must also be set,

	 * but we didn't debug actual testcases to find it out.

	 *

	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 */

	I915_WRITE(GEN6_UCGCTL2,

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);



	/* This is required by WaCatErrorRejectionIssue */

	/* This is required by WaCatErrorRejectionIssue */

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
@@ -3449,11 +3465,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);





	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 */

	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);

	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);





	I915_WRITE(IVB_CHICKEN3,

	I915_WRITE(IVB_CHICKEN3,
@@ -3473,6 +3484,29 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);

		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);







	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

	 * gating disable must be set.  Failure to set it results in

	 * flickering pixels due to Z write ordering failures after

	 * some amount of runtime in the Mesa "fire" demo, and Unigine

	 * Sanctuary and Tropics, and apparently anything else with

	 * alpha test or pixel discard.

	 *

	 * According to the spec, bit 11 (RCCUNIT) must also be set,

	 * but we didn't debug actual testcases to find it out.

	 *

	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 *

	 * Also apply WaDisableVDSUnitClockGating and

	 * WaDisableRCPBUnitClockGating.

	 */

	I915_WRITE(GEN6_UCGCTL2,

		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);



	for_each_pipe(pipe) {

	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   I915_READ(DSPCNTR(pipe)) |