Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0f531431 authored by Mathias Nyman's avatar Mathias Nyman Committed by Ingo Molnar
Browse files

x86/intel/lpss: Add pin control support to Intel low power subsystem 



x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.

At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol
functions such as pin muxing and grouping are possible to add
later.

Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: http://lkml.kernel.org/r/1379080949-21734-1-git-send-email-mathias.nyman@linux.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 9d8e3f96

arch/x86/Kconfig

+3 −2
Original line number Diff line number Diff line
@@ -482,11 +482,12 @@ config X86_INTEL_LPSS 
	bool "Intel Low Power Subsystem Support"

	depends on ACPI

	select COMMON_CLK

	select PINCTRL

	---help---

	  Select to build support for Intel Low Power Subsystem such as

	  found on Intel Lynxpoint PCH. Selecting this option enables

	  things like clock tree (common clock framework) which are needed

	  by the LPSS peripheral drivers.

	  things like clock tree (common clock framework) and pincontrol

	  which are needed by the LPSS peripheral drivers.



config X86_RDC321X

	bool "RDC R-321x SoC"