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Commit 0f369103 authored by Michael Ellerman's avatar Michael Ellerman Committed by Benjamin Herrenschmidt
Browse files

powerpc: Remove power3 from comments



There are still a few occurences where it remains, because it helps to
explain something that persists.

Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 086dddc1
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@@ -461,8 +461,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
/*
 * Routine to copy a whole page of data, optimized for POWER4.
 * On POWER4 it is more than 50% faster than the simple loop
 * above (following the .Ldst_aligned label) but it runs slightly
 * slower on POWER3.
 * above (following the .Ldst_aligned label).
 */
.Lcopy_page_4K:
	std	r31,-32(1)
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@@ -2,7 +2,7 @@
 * This file contains the routines for handling the MMU on those
 * PowerPC implementations where the MMU substantially follows the
 * architecture specification.  This includes the 6xx, 7xx, 7xxx,
 * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
 * and 8260 implementations but excludes the 8xx and 4xx.
 *  -- paulus
 *
 *  Derived from arch/ppc/mm/init.c:
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@@ -2,7 +2,7 @@
 * This file contains the routines for handling the MMU on those
 * PowerPC implementations where the MMU substantially follows the
 * architecture specification.  This includes the 6xx, 7xx, 7xxx,
 * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
 * and 8260 implementations but excludes the 8xx and 4xx.
 *  -- paulus
 *
 *  Derived from arch/ppc/mm/init.c:
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@@ -61,7 +61,7 @@ choice
	help
	  There are two families of 64 bit PowerPC chips supported.
	  The most common ones are the desktop and server CPUs
	  (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)
	  (POWER4, POWER5, 970, POWER5+, POWER6, POWER7, POWER8 ...)

	  The other are the "embedded" processors compliant with the
	  "Book 3E" variant of the architecture