Commit 0f1bc12e authored Mar 14, 2013 by Thierry Reding Committed by Mike Turquette Apr 01, 2013

clk: tegra: Allow PLLE training to succeed

Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

parent 07961ac7

drivers/clk/tegra/clk-tegra20.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -703,7 +703,7 @@ static void tegra20_pll_init(void)
	clks[pll_a_out0] = clk;		clks[pll_a_out0] = clk;

	/* PLLE */		/* PLLE */
	clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,		clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
	0, 100000000, &pll_e_params,		0, 100000000, &pll_e_params,
	0, pll_e_freq_table, NULL);		0, pll_e_freq_table, NULL);
	clk_register_clkdev(clk, "pll_e", NULL);		clk_register_clkdev(clk, "pll_e", NULL);