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Commit 0e790100 authored by Alex Shi's avatar Alex Shi
Browse files

Merge tag 'v3.18.39' into linux-linaro-lsk-v3.18 

 This is the 3.18.39 stable release
parents 17c92e2a 6e0f6268

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 18

SUBLEVEL = 38

SUBLEVEL = 39

EXTRAVERSION =

NAME = Diseased Newt

arch/arm/mach-mvebu/coherency.c

+8 −14
Original line number Diff line number Diff line
@@ -315,22 +315,16 @@ static void __init armada_370_coherency_init(struct device_node *np) 
}



/*

 * This ioremap hook is used on Armada 375/38x to ensure that PCIe

 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This

 * is needed as a workaround for a deadlock issue between the PCIe

 * interface and the cache controller.

 * This ioremap hook is used on Armada 375/38x to ensure that all MMIO

 * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is

 * needed for the HW I/O coherency mechanism to work properly without

 * deadlock.

 */

static void __iomem *

armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,

armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,

			 unsigned int mtype, void *caller)

{

	struct resource pcie_mem;



	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);



	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)

	mtype = MT_UNCACHED;



	return __arm_ioremap_caller(phys_addr, size, mtype, caller);

}
@@ -339,7 +333,7 @@ static void __init armada_375_380_coherency_init(struct device_node *np) 
	struct device_node *cache_dn;



	coherency_cpu_base = of_iomap(np, 0);

	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;

	arch_ioremap_caller = armada_wa_ioremap_caller;



	/*

	 * We should switch the PL310 to I/O coherency mode only if

arch/mips/kernel/setup.c

+0 −3
Original line number Diff line number Diff line
@@ -685,9 +685,6 @@ static void __init arch_mem_init(char **cmdline_p) 
	for_each_memblock(reserved, reg)

		if (reg->size != 0)

			reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);



	reserve_bootmem_region(__pa_symbol(&__nosave_begin),

			__pa_symbol(&__nosave_end)); /* Reserve for hibernation */

}



static void __init resource_init(void)

arch/sparc/mm/init_64.c

+0 −8
Original line number Diff line number Diff line
@@ -1300,18 +1300,10 @@ static int __init numa_parse_sun4u(void) 


static int __init bootmem_init_numa(void)

{

	int i, j;

	int err = -1;



	numadbg("bootmem_init_numa()\n");



	/* Some sane defaults for numa latency values */

	for (i = 0; i < MAX_NUMNODES; i++) {

		for (j = 0; j < MAX_NUMNODES; j++)

			numa_latency[i][j] = (i == j) ?

				LOCAL_DISTANCE : REMOTE_DISTANCE;

	}



	if (numa_enabled) {

		if (tlb_type == hypervisor)

			err = numa_parse_mdesc();

arch/x86/kernel/early-quirks.c

+92 −13
Original line number Diff line number Diff line
@@ -11,7 +11,11 @@ 


#include <linux/pci.h>

#include <linux/acpi.h>

#include <linux/delay.h>

#include <linux/dmi.h>

#include <linux/pci_ids.h>

#include <linux/bcma/bcma.h>

#include <linux/bcma/bcma_regs.h>

#include <drm/i915_drm.h>

#include <asm/pci-direct.h>

#include <asm/dma.h>
@@ -21,6 +25,9 @@ 
#include <asm/iommu.h>

#include <asm/gart.h>

#include <asm/irq_remapping.h>

#include <asm/early_ioremap.h>



#define dev_err(msg)  pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)



static void __init fix_hypertransport_config(int num, int slot, int func)

{
@@ -75,6 +82,13 @@ static void __init nvidia_bugs(int num, int slot, int func) 
{

#ifdef CONFIG_ACPI

#ifdef CONFIG_X86_IO_APIC

	/*

	 * Only applies to Nvidia root ports (bus 0) and not to

	 * Nvidia graphics cards with PCI ports on secondary buses.

	 */

	if (num)

		return;



	/*

	 * All timer overrides on Nvidia are

	 * wrong unless HPET is enabled.
@@ -565,6 +579,61 @@ static void __init force_disable_hpet(int num, int slot, int func) 
#endif

}



#define BCM4331_MMIO_SIZE	16384

#define BCM4331_PM_CAP		0x40

#define bcma_aread32(reg)	ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)

#define bcma_awrite32(reg, val)	iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)



static void __init apple_airport_reset(int bus, int slot, int func)

{

	void __iomem *mmio;

	u16 pmcsr;

	u64 addr;

	int i;



	if (!dmi_match(DMI_SYS_VENDOR, "Apple Inc."))

		return;



	/* Card may have been put into PCI_D3hot by grub quirk */

	pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);



	if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {

		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;

		write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);

		mdelay(10);



		pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);

		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {

			dev_err("Cannot power up Apple AirPort card\n");

			return;

		}

	}



	addr  =      read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);

	addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;

	addr &= PCI_BASE_ADDRESS_MEM_MASK;



	mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);

	if (!mmio) {

		dev_err("Cannot iomap Apple AirPort card\n");

		return;

	}



	pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");



	for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)

		udelay(10);



	bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);

	bcma_aread32(BCMA_RESET_CTL);

	udelay(1);



	bcma_awrite32(BCMA_RESET_CTL, 0);

	bcma_aread32(BCMA_RESET_CTL);

	udelay(10);



	early_iounmap(mmio, BCM4331_MMIO_SIZE);

}



#define QFLAG_APPLY_ONCE 	0x1

#define QFLAG_APPLIED		0x2
@@ -578,12 +647,6 @@ struct chipset { 
	void (*f)(int num, int slot, int func);

};



/*

 * Only works for devices on the root bus. If you add any devices

 * not on bus 0 readd another loop level in early_quirks(). But

 * be careful because at least the Nvidia quirk here relies on

 * only matching on bus 0.

 */

static struct chipset early_qrk[] __initdata = {

	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,

	  PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
@@ -609,9 +672,13 @@ static struct chipset early_qrk[] __initdata = { 
	 */

	{ PCI_VENDOR_ID_INTEL, 0x0f00,

		PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},

	{ PCI_VENDOR_ID_BROADCOM, 0x4331,

	  PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},

	{}

};



static void __init early_pci_scan_bus(int bus);



/**

 * check_dev_quirk - apply early quirks to a given PCI device

 * @num: bus number
@@ -620,7 +687,7 @@ static struct chipset early_qrk[] __initdata = { 
 *

 * Check the vendor & device ID against the early quirks table.

 *

 * If the device is single function, let early_quirks() know so we don't

 * If the device is single function, let early_pci_scan_bus() know so we don't

 * poke at this device again.

 */

static int __init check_dev_quirk(int num, int slot, int func)
@@ -629,6 +696,7 @@ static int __init check_dev_quirk(int num, int slot, int func) 
	u16 vendor;

	u16 device;

	u8 type;

	u8 sec;

	int i;



	class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
@@ -656,25 +724,36 @@ static int __init check_dev_quirk(int num, int slot, int func) 


	type = read_pci_config_byte(num, slot, func,

				    PCI_HEADER_TYPE);



	if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {

		sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);

		if (sec > num)

			early_pci_scan_bus(sec);

	}



	if (!(type & 0x80))

		return -1;



	return 0;

}



void __init early_quirks(void)

static void __init early_pci_scan_bus(int bus)

{

	int slot, func;



	if (!early_pci_allowed())

		return;



	/* Poor man's PCI discovery */

	/* Only scan the root bus */

	for (slot = 0; slot < 32; slot++)

		for (func = 0; func < 8; func++) {

			/* Only probe function 0 on single fn devices */

			if (check_dev_quirk(0, slot, func))

			if (check_dev_quirk(bus, slot, func))

				break;

		}

}



void __init early_quirks(void)

{

	if (!early_pci_allowed())

		return;



	early_pci_scan_bus(0);

}