Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0e45917b authored by Gustavo Solaira's avatar Gustavo Solaira
Browse files

msm: pcie: Add support for sdxhedgehog 



Add support to enable PCIe Root Complex mode on sdxhedgehog.

Change-Id: I905b620d49915d44e8d61d4ca05dc0301b84cdf0
Signed-off-by: default avatarGustavo Solaira <gustavos@codeaurora.org>
parent 6bb245bb

drivers/pci/host/pci-msm.c

+31 −3
Original line number Diff line number Diff line
@@ -46,7 +46,20 @@ 
#include <linux/ipc_logging.h>

#include <linux/msm_pcie.h>



#ifdef CONFIG_ARCH_MDMCALIFORNIUM

#ifdef CONFIG_ARCH_SDXHEDGEHOG

#define PCIE_VENDOR_ID_RCP		0x17cb

#define PCIE_DEVICE_ID_RCP		0x0303



#define PCIE20_PARF_DBI_BASE_ADDR	0x350

#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE	0x358



#define PCIE_N_PCS_STATUS(n, m)			(PCS_PORT(n, m) + 0x174)



#define TX_BASE 0x200

#define RX_BASE 0x400

#define PCS_BASE 0x800

#define PCS_MISC_BASE 0x600

#elif defined(CONFIG_ARCH_MDMCALIFORNIUM)

#define PCIE_VENDOR_ID_RCP		0x17cb

#define PCIE_DEVICE_ID_RCP		0x0302
@@ -210,6 +223,7 @@ 
#define PCIE_COM_DEBUG_BUS_3_STATUS	0x468



#define PCIE20_PARF_SYS_CTRL	     0x00

#define PCIE20_PARF_PM_CTRL	0x20

#define PCIE20_PARF_PM_STTS		0x24

#define PCIE20_PARF_PCS_DEEMPH	   0x34

#define PCIE20_PARF_PCS_SWING	    0x38
@@ -226,6 +240,7 @@ 
#define PCIE20_PARF_SID_OFFSET		0x234

#define PCIE20_PARF_BDF_TRANSLATE_CFG	0x24C

#define PCIE20_PARF_BDF_TRANSLATE_N	0x250

#define PCIE20_PARF_DEVICE_TYPE	0x1000



#define PCIE20_ELBI_VERSION		0x00

#define PCIE20_ELBI_SYS_CTRL	     0x04
@@ -1043,6 +1058,12 @@ static void pcie_phy_dump(struct msm_pcie_dev_t *dev) 
	int i, size;

	u32 write_val;



	if (dev->phy_ver >= 0x20) {

		PCIE_DUMP(dev, "PCIe: RC%d PHY dump is not supported\n",

			dev->rc_idx);

		return;

	}



	PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx);



	pcie_phy_dump_test_cntrl(dev, 0x18, 0x19, 0x1A, 0x1B);
@@ -1525,7 +1546,7 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) 
	struct msm_pcie_phy_info_t *phy_seq;

	u8 common_phy;



	if (dev->phy_ver == 0x90)

	if (dev->phy_ver >= 0x20)

		return;



	PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx);
@@ -1638,7 +1659,7 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) 


static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)

{

	if (dev->phy_ver == 0x90) {

	if (dev->phy_ver >= 0x20) {

		if (readl_relaxed(dev->phy +

			PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) &

			BIT(6))
@@ -4296,6 +4317,13 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
		msm_pcie_restore_sec_config(dev);

	}



	/* configure PCIe to RC mode */

	msm_pcie_write_reg(dev->parf, PCIE20_PARF_DEVICE_TYPE, 0x4);



	/* enable l1 mode, clear bit 5 (REQ_NOT_ENTR_L1) */

	if (dev->l1_supported)

		msm_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);



	/* enable PCIe clocks and resets */

	msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);