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Commit 0e0f092e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie.

Small fixes for (mostly Nouveau, some radeon) regressions.

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/nouveau: use the correct fence implementation for nv50
  drm/radeon: add new SI pci id
  radeon: add AGPMode 1 quirk for RV250
  drm/radeon: properly track the crtc not_enabled case evergreen_mc_stop()
  drm/nouveau/bios: fix DCB v1.5 parsing
  drm/nouveau: add missing pll_calc calls
  drm/nouveau: fix crash with noaccel=1
  drm/nv40: allocate ctxprog with kmalloc
  drm/nvc0/disp: fix thinko in vblank regression fix..
parents ef6c5be6 452f1920

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+12 −7
Original line number Original line Diff line number Diff line
@@ -49,13 +49,7 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) 
		if (chan->vblank.crtc != crtc)

		if (chan->vblank.crtc != crtc)

			continue;

			continue;





		if (nv_device(priv)->chipset == 0x50) {

		if (nv_device(priv)->chipset >= 0xc0) {

			nv_wr32(priv, 0x001704, chan->vblank.channel);

			nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);

			bar->flush(bar);

			nv_wr32(priv, 0x001570, chan->vblank.offset);

			nv_wr32(priv, 0x001574, chan->vblank.value);

		} else {

			nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);

			nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);

			bar->flush(bar);

			bar->flush(bar);

			nv_wr32(priv, 0x06000c,

			nv_wr32(priv, 0x06000c,
@@ -63,6 +57,17 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) 
			nv_wr32(priv, 0x060010,

			nv_wr32(priv, 0x060010,

				lower_32_bits(chan->vblank.offset));

				lower_32_bits(chan->vblank.offset));

			nv_wr32(priv, 0x060014, chan->vblank.value);

			nv_wr32(priv, 0x060014, chan->vblank.value);

		} else {

			nv_wr32(priv, 0x001704, chan->vblank.channel);

			nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);

			bar->flush(bar);

			if (nv_device(priv)->chipset == 0x50) {

				nv_wr32(priv, 0x001570, chan->vblank.offset);

				nv_wr32(priv, 0x001574, chan->vblank.value);

			} else {

				nv_wr32(priv, 0x060010, chan->vblank.offset);

				nv_wr32(priv, 0x060014, chan->vblank.value);

			}

		}

		}





		list_del(&chan->vblank.head);

		list_del(&chan->vblank.head);

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c

+9 −3
Original line number Original line Diff line number Diff line
@@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) 
			   });

			   });

}

}





void

int

nv40_grctx_init(struct nouveau_device *device, u32 *size)

nv40_grctx_init(struct nouveau_device *device, u32 *size)

{

{

	u32 ctxprog[256], i;

	u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;

	struct nouveau_grctx ctx = {

	struct nouveau_grctx ctx = {

		.device = device,

		.device = device,

		.mode = NOUVEAU_GRCTX_PROG,

		.mode = NOUVEAU_GRCTX_PROG,

		.data = ctxprog,

		.data = ctxprog,

		.ctxprog_max = ARRAY_SIZE(ctxprog)

		.ctxprog_max = 256,

	};

	};





	if (!ctxprog)

		return -ENOMEM;



	nv40_grctx_generate(&ctx);

	nv40_grctx_generate(&ctx);





	nv_wr32(device, 0x400324, 0);

	nv_wr32(device, 0x400324, 0);

	for (i = 0; i < ctx.ctxprog_len; i++)

	for (i = 0; i < ctx.ctxprog_len; i++)

		nv_wr32(device, 0x400328, ctxprog[i]);

		nv_wr32(device, 0x400328, ctxprog[i]);

	*size = ctx.ctxvals_pos * 4;

	*size = ctx.ctxvals_pos * 4;



	kfree(ctxprog);

	return 0;

}
 
}

drivers/gpu/drm/nouveau/core/engine/graph/nv40.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object) 
		return ret;

		return ret;





	/* generate and upload context program */

	/* generate and upload context program */

	nv40_grctx_init(nv_device(priv), &priv->size);

	ret = nv40_grctx_init(nv_device(priv), &priv->size);

	if (ret)

		return ret;





	/* No context present currently */

	/* No context present currently */

	nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

drivers/gpu/drm/nouveau/core/engine/graph/nv40.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -15,7 +15,7 @@ nv44_graph_class(void *priv) 
	return !(0x0baf & (1 << (device->chipset & 0x0f)));

	return !(0x0baf & (1 << (device->chipset & 0x0f)));

}

}





void nv40_grctx_init(struct nouveau_device *, u32 *size);

int  nv40_grctx_init(struct nouveau_device *, u32 *size);

void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);

void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);





#endif
 
#endif

drivers/gpu/drm/nouveau/core/include/core/object.h

+9 −5
Original line number Original line Diff line number Diff line
@@ -175,14 +175,18 @@ nv_mo32(void *obj, u32 addr, u32 mask, u32 data) 
	return temp;

	return temp;

}

}





static inline bool

static inline int

nv_strncmp(void *obj, u32 addr, u32 len, const char *str)

nv_memcmp(void *obj, u32 addr, const char *str, u32 len)

{

{

	unsigned char c1, c2;



	while (len--) {

	while (len--) {

		if (nv_ro08(obj, addr++) != *(str++))

		c1 = nv_ro08(obj, addr++);

			return false;

		c2 = *(str++);

		if (c1 != c2)

			return c1 - c2;

	}

	}

	return true;

	return 0;

}

}





#endif
 
#endif