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Commit 0de038a9 authored by Anusha Koduru's avatar Anusha Koduru
Browse files

mdss: mdp: modify MISR offset for 8952 



Additional offset is needed for MISR CTRL and SIGNATURE
registers on 8952. Add the required offset of 0x10.
Also add logic to select appropriate registers for video
and command mode.

Change-Id: I148200bdac98dfb446d7958ab700ed221e3d48d0
Signed-off-by: default avatarAnusha Koduru <kanusha@codeaurora.org>
parent 09deb55f

drivers/video/msm/mdss/mdss_debug.c

+16 −4
Original line number Diff line number Diff line
@@ -1226,16 +1226,28 @@ static inline struct mdss_mdp_misr_map *mdss_misr_get_map(u32 block_id, 
			if (block_id <= DISPLAY_MISR_HDMI) {

				intf_base = (char *)mdss_mdp_get_intf_base_addr(

						mdata, block_id);

				ctrl_reg = intf_base + MDSS_MDP_INTF_MISR_CTRL;



				if ((block_id == DISPLAY_MISR_DSI0 ||

				     block_id == DISPLAY_MISR_DSI1) &&

				     (ctl && !ctl->is_video_mode)) {

					ctrl_reg = intf_base +

						MDSS_MDP_INTF_CMD_MISR_CTRL;

					value_reg = intf_base +

					    MDSS_MDP_INTF_CMD_MISR_SIGNATURE;

				} else {

					ctrl_reg = intf_base +

						MDSS_MDP_INTF_MISR_CTRL;

					value_reg = intf_base +

						MDSS_MDP_INTF_MISR_SIGNATURE;

				}

			}

			/*

			 * For msm8916/8939, additional offset of 0x10

			 * is required

			 */

			if ((mdata->mdp_rev == MDSS_MDP_HW_REV_106) ||

				(mdata->mdp_rev == MDSS_MDP_HW_REV_108)) {

				(mdata->mdp_rev == MDSS_MDP_HW_REV_108) ||

				(mdata->mdp_rev == MDSS_MDP_HW_REV_112)) {

				ctrl_reg += 0x10;

				value_reg += 0x10;

			}

drivers/video/msm/mdss/mdss_mdp_hwio.h

+4 −0
Original line number Diff line number Diff line
@@ -653,6 +653,8 @@ enum mdss_mdp_pingpong_index { 


#define MDSS_MDP_INTF_MISR_CTRL		0x180

#define MDSS_MDP_INTF_MISR_SIGNATURE		(MDSS_MDP_INTF_MISR_CTRL + 0x4)

#define MDSS_MDP_INTF_CMD_MISR_CTRL		(MDSS_MDP_INTF_MISR_CTRL + 0x8)

#define MDSS_MDP_INTF_CMD_MISR_SIGNATURE	(MDSS_MDP_INTF_MISR_CTRL + 0xC)



#define MDSS_MDP_REG_CDM_CSC_10_OPMODE                  0x000

#define MDSS_MDP_REG_CDM_CSC_10_BASE                    0x004
@@ -675,6 +677,8 @@ enum mdss_mdp_pingpong_index { 


/* Following offsets are with respect to MDP base */

#define MDSS_MDP_MDP_OUT_CTL_0                          0x410

#define MDSS_MDP_INTF_CMD_MISR_CTRL		(MDSS_MDP_INTF_MISR_CTRL + 0x8)

#define MDSS_MDP_INTF_CMD_MISR_SIGNATURE	(MDSS_MDP_INTF_MISR_CTRL + 0xC)

/* following offsets are with respect to MDP VBIF base */

#define MMSS_VBIF_CLKON			0x4

#define MMSS_VBIF_RD_LIM_CONF			0x0B0