MIPS: Netlogic: Move code common with XLP to common/ (0c965407) · Commits · e / devices / android_kernel_xiaomi_markw

arch/mips/include/asm/netlogic/common.h

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			/*
			* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
			* reserved.
			*
			* This software is available to you under a choice of one of two
			* licenses. You may choose to be licensed under the terms of the GNU
			* General Public License (GPL) Version 2, available from the file
			* COPYING in the main directory of this source tree, or the NetLogic
			* license below:
			*
			* Redistribution and use in source and binary forms, with or without
			* modification, are permitted provided that the following conditions
			* are met:
			*
			* 1. Redistributions of source code must retain the above copyright
			* notice, this list of conditions and the following disclaimer.
			* 2. Redistributions in binary form must reproduce the above copyright
			* notice, this list of conditions and the following disclaimer in
			* the documentation and/or other materials provided with the
			* distribution.
			*
			* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
			* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
			* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
			* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
			* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
			* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
			* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
			* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
			* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
			* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
			*/

			#ifndef _NETLOGIC_COMMON_H_
			#define _NETLOGIC_COMMON_H_

			/*
			* Common SMP definitions
			*/
			struct irq_desc;
			extern struct plat_smp_ops nlm_smp_ops;
			extern char nlm_reset_entry[], nlm_reset_entry_end[];
			void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
			void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
			void nlm_smp_irq_init(void);
			void prom_pre_boot_secondary_cpus(void);
			int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
			void nlm_boot_smp_nmi(void);

			/*
			* Misc.
			*/
			extern unsigned long nlm_common_ebase;
			unsigned int nlm_get_cpu_frequency(void);
			#endif /* _NETLOGIC_COMMON_H_ */

arch/mips/include/asm/netlogic/haldefs.h

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			/*
			* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
			* reserved.
			*
			* This software is available to you under a choice of one of two
			* licenses. You may choose to be licensed under the terms of the GNU
			* General Public License (GPL) Version 2, available from the file
			* COPYING in the main directory of this source tree, or the NetLogic
			* license below:
			*
			* Redistribution and use in source and binary forms, with or without
			* modification, are permitted provided that the following conditions
			* are met:
			*
			* 1. Redistributions of source code must retain the above copyright
			* notice, this list of conditions and the following disclaimer.
			* 2. Redistributions in binary form must reproduce the above copyright
			* notice, this list of conditions and the following disclaimer in
			* the documentation and/or other materials provided with the
			* distribution.
			*
			* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
			* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
			* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
			* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
			* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
			* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
			* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
			* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
			* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
			* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
			*/

			#ifndef __NLM_HAL_HALDEFS_H__
			#define __NLM_HAL_HALDEFS_H__

			/*
			* This file contains platform specific memory mapped IO implementation
			* and will provide a way to read 32/64 bit memory mapped registers in
			* all ABIs
			*/
			/*
			* For o32 compilation, we have to disable interrupts and enable KX bit to
			* access 64 bit addresses or data.
			*
			* We need to disable interrupts because we save just the lower 32 bits of
			* registers in interrupt handling. So if we get hit by an interrupt while
			* using the upper 32 bits of a register, we lose.
			*/
			static inline uint32_t nlm_save_flags_kx(void)
			{
			return change_c0_status(ST0_KX \| ST0_IE, ST0_KX);
			}

			static inline uint32_t nlm_save_flags_cop2(void)
			{
			return change_c0_status(ST0_CU2 \| ST0_IE, ST0_CU2);
			}

			static inline void nlm_restore_flags(uint32_t sr)
			{
			write_c0_status(sr);
			}

			/*
			* The n64 implementations are simple, the o32 implementations when they
			* are added, will have to disable interrupts and enable KX before doing
			* 64 bit ops.
			*/
			static inline uint32_t
			nlm_read_reg(uint64_t base, uint32_t reg)
			{
			volatile uint32_t addr = (volatile uint32_t )(long)base + reg;

			return *addr;
			}

			static inline void
			nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
			{
			volatile uint32_t addr = (volatile uint32_t )(long)base + reg;

			*addr = val;
			}

			static inline uint64_t
			nlm_read_reg64(uint64_t base, uint32_t reg)
			{
			uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
			volatile uint64_t ptr = (volatile uint64_t )(long)addr;

			return *ptr;
			}

			static inline void
			nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
			{
			uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
			volatile uint64_t ptr = (volatile uint64_t )(long)addr;

			*ptr = val;
			}

			/*
			* Routines to store 32/64 bit values to 64 bit addresses,
			* used when going thru XKPHYS to access registers
			*/
			static inline uint32_t
			nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
			{
			return nlm_read_reg(base, reg);
			}

			static inline void
			nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
			{
			nlm_write_reg(base, reg, val);
			}

			static inline uint64_t
			nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
			{
			return nlm_read_reg64(base, reg);
			}

			static inline void
			nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
			{
			nlm_write_reg64(base, reg, val);
			}

			/* Location where IO base is mapped */
			extern uint64_t nlm_io_base;

			static inline uint64_t
			nlm_mmio_base(uint32_t devoffset)
			{
			return nlm_io_base + devoffset;
			}

			#endif

arch/mips/include/asm/netlogic/xlr/iomap.h

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	@@ -106,26 +106,4 @@
	#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000		#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
	#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000		#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000

	#ifndef __ASSEMBLY__
	#include <linux/types.h>
	#include <asm/byteorder.h>

	typedef volatile __u32 nlm_reg_t;
	extern unsigned long netlogic_io_base;

	/* FIXME read once in write_reg */
	#ifdef CONFIG_CPU_LITTLE_ENDIAN
	#define netlogic_read_reg(base, offset) ((base)[(offset)])
	#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
	#else
	#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
	#define netlogic_write_reg(base, offset, value) \
	((base)[(offset)] = cpu_to_be32((value)))
	#endif

	#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
	#define netlogic_write_reg_le32(base, offset, value) \
	((base)[(offset)] = cpu_to_le32((value)))
	#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
	#endif /* __ASSEMBLY__ */
	#endif		#endif

arch/mips/include/asm/netlogic/xlr/pic.h

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	@@ -193,39 +193,72 @@
	/* end XLS */		/* end XLS */

	#ifndef __ASSEMBLY__		#ifndef __ASSEMBLY__
	static inline void pic_send_ipi(u32 ipi)
			#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
			((irq) <= PIC_TIMER_7_IRQ))
			#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
			((irq) <= PIC_IRT_LAST_IRQ))

			static inline int
			nlm_irq_to_irt(int irq)
	{		{
	nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);		if (PIC_IRQ_IS_IRT(irq) == 0)
			return -1;

	netlogic_write_reg(mmio, PIC_IPI, ipi);		return PIC_IRQ_TO_INTR(irq);
	}		}

	static inline u32 pic_read_control(void)		static inline int
			nlm_irt_to_irq(int irt)
	{		{
	nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);

	return netlogic_read_reg(mmio, PIC_CTRL);		return PIC_INTR_TO_IRQ(irt);
	}		}

	static inline void pic_write_control(u32 control)		static inline void
			nlm_pic_enable_irt(uint64_t base, int irt)
	{		{
	nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);		uint32_t reg;

	netlogic_write_reg(mmio, PIC_CTRL, control);		reg = nlm_read_reg(base, PIC_IRT_1(irt));
			nlm_write_reg(base, PIC_IRT_1(irt), reg \| (1u << 31));
	}		}

	static inline void pic_update_control(u32 control)		static inline void
			nlm_pic_disable_irt(uint64_t base, int irt)
	{		{
	nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);		uint32_t reg;

	netlogic_write_reg(mmio, PIC_CTRL,		reg = nlm_read_reg(base, PIC_IRT_1(irt));
	(control \| netlogic_read_reg(mmio, PIC_CTRL)));		nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
	}		}

	#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \		static inline void
	((irq) <= PIC_TIMER_7_IRQ))		nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
	#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \		{
	((irq) <= PIC_IRT_LAST_IRQ))		unsigned int tid, pid;
	#endif
			tid = hwt & 0x3;
			pid = (hwt >> 2) & 0x07;
			nlm_write_reg(base, PIC_IPI,
			(pid << 20) \| (tid << 16) \| (nmi << 8) \| irq);
			}

			static inline void
			nlm_pic_ack(uint64_t base, int irt)
			{
			nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
			}

			static inline void
			nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
			{
			nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
			/* local scheduling, invalid, level by default */
			nlm_write_reg(base, PIC_IRT_1(irt),
			(1 << 30) \| (1 << 6) \| irq);
			}

			extern uint64_t nlm_pic_base;
			#endif
	#endif /* _ASM_NLM_XLR_PIC_H */		#endif /* _ASM_NLM_XLR_PIC_H */

arch/mips/include/asm/netlogic/xlr/xlr.h

+0 −11

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	@@ -40,17 +40,6 @@ struct uart_port;
	unsigned int nlm_xlr_uart_in(struct uart_port *, int);		unsigned int nlm_xlr_uart_in(struct uart_port *, int);
	void nlm_xlr_uart_out(struct uart_port *, int, int);		void nlm_xlr_uart_out(struct uart_port *, int, int);

	/* SMP support functions */
	struct irq_desc;
	void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
	void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
	int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
	void nlm_smp_irq_init(void);
	void nlm_boot_smp_nmi(void);
	void prom_pre_boot_secondary_cpus(void);

	extern struct plat_smp_ops nlm_smp_ops;
	extern unsigned long nlm_common_ebase;

	/* XLS B silicon "Rook" */		/* XLS B silicon "Rook" */
	static inline unsigned int nlm_chip_is_xls_b(void)		static inline unsigned int nlm_chip_is_xls_b(void)