Merge tag 'mvebu_everything_for_3.8' of git://git.infradead.org/users/jcooper/linux into late/mvebu

- interrupt-controller: Identifies the node as an interrupt controller.

- #interrupt-cells: The number of cells to define the interrupts. Should be 1.

  The cell is the IRQ number

- reg: Should contain PMIC registers location and length. First pair

  for the main interrupt registers, second pair for the per-CPU

  interrupt registers

  interrupt registers. For this last pair, to be compliant with SMP

  support, the "virtual" must be use (For the record, these registers

  automatically map to the interrupt controller registers of the

  current CPU)

Example:

              #address-cells = <1>;

              #size-cells = <1>;

              interrupt-controller;

              reg = <0xd0020000 0x1000>,

                    <0xd0021000 0x1000>;

              reg = <0xd0020a00 0x1d0>,

                    <0xd0021070 0x58>;

        };

Power Management Service Unit(PMSU)

-----------------------------------

Available on Marvell SOCs: Armada 370 and Armada XP

Required properties:

- compatible: "marvell,armada-370-xp-pmsu"

- reg: Should contain PMSU registers location and length. First pair

  for the per-CPU SW Reset Control registers, second pair for the

  Power Management Service Unit.

Example:

armada-370-xp-pmsu@d0022000 {

	compatible = "marvell,armada-370-xp-pmsu";

	reg = <0xd0022100 0x430>,

	      <0xd0020800 0x20>;

};

- compatible: Should be "marvell,armada-370-xp-timer"

- interrupts: Should contain the list of Global Timer interrupts

- reg: Should contain the base address of the Global Timer registers

- clocks: clock driving the timer hardware

Optional properties:

- marvell,timer-25Mhz: Tells whether the Global timer supports the 25

Coherency fabric

----------------

Available on Marvell SOCs: Armada 370 and Armada XP

Required properties:

- compatible: "marvell,coherency-fabric"

- reg: Should contain coherency fabric registers location and

  length. First pair for the coherency fabric registers, second pair

  for the per-CPU fabric registers registers.

Example:

coherency-fabric@d0020200 {

	compatible = "marvell,coherency-fabric";

	reg = <0xd0020200 0xb0>,

		<0xd0021810 0x1c>;

};

* Core Clock bindings for Marvell MVEBU SoCs

Marvell MVEBU SoCs usually allow to determine core clock frequencies by

reading the Sample-At-Reset (SAR) register. The core clock consumer should

specify the desired clock by having the clock ID in its "clocks" phandle cell.

The following is a list of provided IDs and clock names on Armada 370/XP:

 0 = tclk    (Internal Bus clock)

 1 = cpuclk  (CPU clock)

 2 = nbclk   (L2 Cache clock)

 3 = hclk    (DRAM control clock)

 4 = dramclk (DDR clock)

The following is a list of provided IDs and clock names on Kirkwood and Dove:

 0 = tclk   (Internal Bus clock)

 1 = cpuclk (CPU0 clock)

 2 = l2clk  (L2 Cache clock derived from CPU0 clock)

 3 = ddrclk (DDR controller clock derived from CPU0 clock)

Required properties:

- compatible : shall be one of the following:

	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks

	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks

	"marvell,dove-core-clock" - for Dove SoC core clocks

	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC

- reg : shall be the register address of the Sample-At-Reset (SAR) register

- #clock-cells : from common clock binding; shall be set to 1

Optional properties:

- clock-output-names : from common clock binding; allows overwrite default clock

	output names ("tclk", "cpuclk", "l2clk", "ddrclk")

Example:

core_clk: core-clocks@d0214 {

	compatible = "marvell,dove-core-clock";

	reg = <0xd0214 0x4>;

	#clock-cells = <1>;

};

spi0: spi@10600 {

	compatible = "marvell,orion-spi";

	/* ... */

	/* get tclk from core clock provider */

	clocks = <&core_clk 0>;

};