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Commit 0bfdbf0e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "Two small fixes for 3.12 only this week.  I have a few more fixes
  pending but those are conceptually more complex so will have to wait
  for a bit longer"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Fix forgotten preempt_enable() when CPU has inclusive pcaches
  MIPS: Alchemy: MTX-1: fix incorrect placement of __initdata tag
parents 413df1cb 5596b0b2

arch/mips/alchemy/board-mtx1.c

+1 −1
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ static struct platform_device mtx1_pci_host = { 
	.resource	= alchemy_pci_host_res,

};



static struct __initdata platform_device * mtx1_devs[] = {

static struct platform_device *mtx1_devs[] __initdata = {

	&mtx1_pci_host,

	&mtx1_gpio_leds,

	&mtx1_wdt,

arch/mips/mm/c-r4k.c

+2 −0
Original line number Diff line number Diff line
@@ -609,6 +609,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 
			r4k_blast_scache();

		else

			blast_scache_range(addr, addr + size);

		preempt_enable();

		__sync();

		return;

	}
@@ -650,6 +651,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 
			 */

			blast_inv_scache_range(addr, addr + size);

		}

		preempt_enable();

		__sync();

		return;

	}