[ARM] cputype: separate definitions, use them (0ba8b9b2) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/include/asm/cputype.h

0 → 100644

+64 −0

Original line number	Original line	Diff line number	Diff line
			#ifndef __ASM_ARM_CPUTYPE_H
			#define __ASM_ARM_CPUTYPE_H

			#include <linux/stringify.h>

			#define CPUID_ID 0
			#define CPUID_CACHETYPE 1
			#define CPUID_TCM 2
			#define CPUID_TLBTYPE 3

			#ifdef CONFIG_CPU_CP15
			#define read_cpuid(reg) \
			({ \
			unsigned int __val; \
			asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
			: "=r" (__val) \
			: \
			: "cc"); \
			__val; \
			})
			#else
			extern unsigned int processor_id;
			#define read_cpuid(reg) (processor_id)
			#endif

			/*
			* The CPU ID never changes at run time, so we might as well tell the
			* compiler that it's constant. Use this function to read the CPU ID
			* rather than directly reading processor_id or read_cpuid() directly.
			*/
			static inline unsigned int __attribute_const__ read_cpuid_id(void)
			{
			return read_cpuid(CPUID_ID);
			}

			static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
			{
			return read_cpuid(CPUID_CACHETYPE);
			}

			/*
			* Intel's XScale3 core supports some v6 features (supersections, L2)
			* but advertises itself as v5 as it does not support the v6 ISA. For
			* this reason, we need a way to explicitly test for this type of CPU.
			*/
			#ifndef CONFIG_CPU_XSC3
			#define cpu_is_xsc3() 0
			#else
			static inline int cpu_is_xsc3(void)
			{
			if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
			return 1;

			return 0;
			}
			#endif

			#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
			#define cpu_is_xscale() 0
			#else
			#define cpu_is_xscale() 1
			#endif

			#endif

arch/arm/include/asm/system.h

+0 −58

Original line number	Original line	Diff line number	Diff line
	@@ -43,11 +43,6 @@
	#define CR_XP (1 << 23) /* Extended page tables */		#define CR_XP (1 << 23) /* Extended page tables */
	#define CR_VE (1 << 24) /* Vectored interrupts */		#define CR_VE (1 << 24) /* Vectored interrupts */

	#define CPUID_ID 0
	#define CPUID_CACHETYPE 1
	#define CPUID_TCM 2
	#define CPUID_TLBTYPE 3

	/*		/*
	* This is used to ensure the compiler did actually allocate the register we		* This is used to ensure the compiler did actually allocate the register we
	* asked it for some inline assembly sequences. Apparently we can't trust		* asked it for some inline assembly sequences. Apparently we can't trust
	@@ -61,36 +56,8 @@
	#ifndef __ASSEMBLY__		#ifndef __ASSEMBLY__

	#include <linux/linkage.h>		#include <linux/linkage.h>
	#include <linux/stringify.h>
	#include <linux/irqflags.h>		#include <linux/irqflags.h>

	#ifdef CONFIG_CPU_CP15
	#define read_cpuid(reg) \
	({ \
	unsigned int __val; \
	asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
	: "=r" (__val) \
	: \
	: "cc"); \
	__val; \
	})
	#else
	extern unsigned int processor_id;
	#define read_cpuid(reg) (processor_id)
	#endif

	/*
	* The CPU ID never changes at run time, so we might as well tell the
	* compiler that it's constant. Use this function to read the CPU ID
	* rather than directly reading processor_id or read_cpuid() directly.
	*/
	static inline unsigned int read_cpuid_id(void) __attribute_const__;

	static inline unsigned int read_cpuid_id(void)
	{
	return read_cpuid(CPUID_ID);
	}

	#define __exception __attribute__((section(".exception.text")))		#define __exception __attribute__((section(".exception.text")))

	struct thread_info;		struct thread_info;
	@@ -131,31 +98,6 @@ extern void cpu_init(void);
	void arm_machine_restart(char mode);		void arm_machine_restart(char mode);
	extern void (*arm_pm_restart)(char str);		extern void (*arm_pm_restart)(char str);

	/*
	* Intel's XScale3 core supports some v6 features (supersections, L2)
	* but advertises itself as v5 as it does not support the v6 ISA. For
	* this reason, we need a way to explicitly test for this type of CPU.
	*/
	#ifndef CONFIG_CPU_XSC3
	#define cpu_is_xsc3() 0
	#else
	static inline int cpu_is_xsc3(void)
	{
	extern unsigned int processor_id;

	if ((processor_id & 0xffffe000) == 0x69056000)
	return 1;

	return 0;
	}
	#endif

	#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
	#define cpu_is_xscale() 0
	#else
	#define cpu_is_xscale() 1
	#endif

	#define UDBG_UNDEFINED (1 << 0)		#define UDBG_UNDEFINED (1 << 0)
	#define UDBG_SYSCALL (1 << 1)		#define UDBG_SYSCALL (1 << 1)
	#define UDBG_BADABORT (1 << 2)		#define UDBG_BADABORT (1 << 2)

arch/arm/kernel/setup.c

+23 −22

Original line number	Original line	Diff line number	Diff line
	@@ -26,6 +26,7 @@
	#include <linux/fs.h>		#include <linux/fs.h>

	#include <asm/cpu.h>		#include <asm/cpu.h>
			#include <asm/cputype.h>
	#include <asm/elf.h>		#include <asm/elf.h>
	#include <asm/procinfo.h>		#include <asm/procinfo.h>
	#include <asm/setup.h>		#include <asm/setup.h>
	@@ -280,9 +281,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)

	static void __init dump_cpu_info(int cpu)		static void __init dump_cpu_info(int cpu)
	{		{
	unsigned int info = read_cpuid(CPUID_CACHETYPE);		unsigned int info = read_cpuid_cachetype();

	if (info != processor_id) {		if (info != read_cpuid_id()) {
	printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",		printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
	cache_types[CACHE_TYPE(info)]);		cache_types[CACHE_TYPE(info)]);
	if (CACHE_S(info)) {		if (CACHE_S(info)) {
	@@ -301,15 +302,15 @@ int cpu_architecture(void)
	{		{
	int cpu_arch;		int cpu_arch;

	if ((processor_id & 0x0008f000) == 0) {		if ((read_cpuid_id() & 0x0008f000) == 0) {
	cpu_arch = CPU_ARCH_UNKNOWN;		cpu_arch = CPU_ARCH_UNKNOWN;
	} else if ((processor_id & 0x0008f000) == 0x00007000) {		} else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
	cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;		cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
	} else if ((processor_id & 0x00080000) == 0x00000000) {		} else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
	cpu_arch = (processor_id >> 16) & 7;		cpu_arch = (read_cpuid_id() >> 16) & 7;
	if (cpu_arch)		if (cpu_arch)
	cpu_arch += CPU_ARCH_ARMv3;		cpu_arch += CPU_ARCH_ARMv3;
	} else if ((processor_id & 0x000f0000) == 0x000f0000) {		} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
	unsigned int mmfr0;		unsigned int mmfr0;

	/* Revised CPUID format. Read the Memory Model Feature		/* Revised CPUID format. Read the Memory Model Feature
	@@ -346,10 +347,10 @@ static void __init setup_processor(void)
	* types. The linker builds this table for us from the		* types. The linker builds this table for us from the
	* entries in arch/arm/mm/proc-*.S		* entries in arch/arm/mm/proc-*.S
	*/		*/
	list = lookup_processor_type(processor_id);		list = lookup_processor_type(read_cpuid_id());
	if (!list) {		if (!list) {
	printk("CPU configuration botched (ID %08x), unable "		printk("CPU configuration botched (ID %08x), unable "
	"to continue.\n", processor_id);		"to continue.\n", read_cpuid_id());
	while (1);		while (1);
	}		}

	@@ -369,7 +370,7 @@ static void __init setup_processor(void)
	#endif		#endif

	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",		printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
	cpu_name, processor_id, (int)processor_id & 15,		cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
	proc_arch[cpu_architecture()], cr_alignment);		proc_arch[cpu_architecture()], cr_alignment);

	sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);		sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
	@@ -922,7 +923,7 @@ static int c_show(struct seq_file m, void v)
	int i;		int i;

	seq_printf(m, "Processor\t: %s rev %d (%s)\n",		seq_printf(m, "Processor\t: %s rev %d (%s)\n",
	cpu_name, (int)processor_id & 15, elf_platform);		cpu_name, read_cpuid_id() & 15, elf_platform);

	#if defined(CONFIG_SMP)		#if defined(CONFIG_SMP)
	for_each_online_cpu(i) {		for_each_online_cpu(i) {
	@@ -949,30 +950,30 @@ static int c_show(struct seq_file m, void v)
	if (elf_hwcap & (1 << i))		if (elf_hwcap & (1 << i))
	seq_printf(m, "%s ", hwcap_str[i]);		seq_printf(m, "%s ", hwcap_str[i]);

	seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);		seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
	seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);		seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);

	if ((processor_id & 0x0008f000) == 0x00000000) {		if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
	/* pre-ARM7 */		/* pre-ARM7 */
	seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);		seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
	} else {		} else {
	if ((processor_id & 0x0008f000) == 0x00007000) {		if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
	/* ARM7 */		/* ARM7 */
	seq_printf(m, "CPU variant\t: 0x%02x\n",		seq_printf(m, "CPU variant\t: 0x%02x\n",
	(processor_id >> 16) & 127);		(read_cpuid_id() >> 16) & 127);
	} else {		} else {
	/* post-ARM7 */		/* post-ARM7 */
	seq_printf(m, "CPU variant\t: 0x%x\n",		seq_printf(m, "CPU variant\t: 0x%x\n",
	(processor_id >> 20) & 15);		(read_cpuid_id() >> 20) & 15);
	}		}
	seq_printf(m, "CPU part\t: 0x%03x\n",		seq_printf(m, "CPU part\t: 0x%03x\n",
	(processor_id >> 4) & 0xfff);		(read_cpuid_id() >> 4) & 0xfff);
	}		}
	seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);		seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);

	{		{
	unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);		unsigned int cache_info = read_cpuid_cachetype();
	if (cache_info != processor_id) {		if (cache_info != read_cpuid_id()) {
	seq_printf(m, "Cache type\t: %s\n"		seq_printf(m, "Cache type\t: %s\n"
	"Cache clean\t: %s\n"		"Cache clean\t: %s\n"
	"Cache lockdown\t: %s\n"		"Cache lockdown\t: %s\n"

arch/arm/mach-iop32x/iq31244.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -27,6 +27,7 @@
	#include <linux/mtd/physmap.h>		#include <linux/mtd/physmap.h>
	#include <linux/platform_device.h>		#include <linux/platform_device.h>
	#include <mach/hardware.h>		#include <mach/hardware.h>
			#include <asm/cputype.h>
	#include <asm/io.h>		#include <asm/io.h>
	#include <asm/irq.h>		#include <asm/irq.h>
	#include <asm/mach/arch.h>		#include <asm/mach/arch.h>
	@@ -49,8 +50,7 @@ static int force_ep80219;

	static int is_80219(void)		static int is_80219(void)
	{		{
	extern int processor_id;		return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
	return !!((processor_id & 0xffffffe0) == 0x69052e20);
	}		}

	static int is_ep80219(void)		static int is_ep80219(void)

arch/arm/mach-ixp4xx/common-pci.c

+3 −4

Original line number	Original line	Diff line number	Diff line
	@@ -27,6 +27,7 @@
	#include <linux/device.h>		#include <linux/device.h>
	#include <asm/dma-mapping.h>		#include <asm/dma-mapping.h>

			#include <asm/cputype.h>
	#include <asm/io.h>		#include <asm/io.h>
	#include <asm/irq.h>		#include <asm/irq.h>
	#include <asm/sizes.h>		#include <asm/sizes.h>
	@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,

	void __init ixp4xx_pci_preinit(void)		void __init ixp4xx_pci_preinit(void)
	{		{
	unsigned long processor_id;		unsigned long cpuid = read_cpuid_id();

	asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);

	/*		/*
	* Determine which PCI read method to use.		* Determine which PCI read method to use.
	* Rev 0 IXP425 requires workaround.		* Rev 0 IXP425 requires workaround.
	*/		*/
	if (!(processor_id & 0xf) && cpu_is_ixp42x()) {		if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
	printk("PCI: IXP42x A0 silicon detected - "		printk("PCI: IXP42x A0 silicon detected - "
	"PCI Non-Prefetch Workaround Enabled\n");		"PCI Non-Prefetch Workaround Enabled\n");
	ixp4xx_pci_read = ixp4xx_pci_read_errata;		ixp4xx_pci_read = ixp4xx_pci_read_errata;