Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0b31e023 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: update line buffer allocation for dce4.1/5 



We need to allocate line buffer to each display when
setting up the watermarks.  Failure to do so can lead
to a blank screen.  This fixes blank screen problems
on dce4.1/5 asics.

Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent e5b9e750

drivers/gpu/drm/radeon/evergreen.c

+21 −4
Original line number Diff line number Diff line
@@ -1812,7 +1812,8 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 
					struct drm_display_mode *mode,

					struct drm_display_mode *other_mode)

{

	u32 tmp;

	u32 tmp, buffer_alloc, i;

	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

	/*

	 * Line Buffer Setup

	 * There are 3 line buffers, each one shared by 2 display controllers.
@@ -1835,18 +1836,34 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 
	 * non-linked crtcs for maximum line buffer allocation.

	 */

	if (radeon_crtc->base.enabled && mode) {

		if (other_mode)

		if (other_mode) {

			tmp = 0; /* 1/2 */

		else

			buffer_alloc = 1;

		} else {

			tmp = 2; /* whole */

	} else

			buffer_alloc = 2;

		}

	} else {

		tmp = 0;

		buffer_alloc = 0;

	}



	/* second controller of the pair uses second half of the lb */

	if (radeon_crtc->crtc_id % 2)

		tmp += 4;

	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);



	if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {

		WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

		       DMIF_BUFFERS_ALLOCATED(buffer_alloc));

		for (i = 0; i < rdev->usec_timeout; i++) {

			if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

			    DMIF_BUFFERS_ALLOCATED_COMPLETED)

				break;

			udelay(1);

		}

	}



	if (radeon_crtc->base.enabled && mode) {

		switch (tmp) {

		case 0:

drivers/gpu/drm/radeon/evergreend.h

+4 −0
Original line number Diff line number Diff line
@@ -1160,6 +1160,10 @@ 
#       define LATENCY_LOW_WATERMARK(x)                   ((x) << 0)

#       define LATENCY_HIGH_WATERMARK(x)                  ((x) << 16)



#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0ca0

#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)

#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)



#define IH_RB_CNTL                                        0x3e00

#       define IH_RB_ENABLE                               (1 << 0)

#       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */