Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 09fb8bd1 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: fix card_posted check for newer asics 



Newer asics have variable numbers of crtcs.  Use that
rather than the asic family to determine which crtcs
to check.  This avoids checking non-existent crtcs or
missing crtcs on certain asics.

Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 468ef1a5

drivers/gpu/drm/radeon/radeon_device.c

+9 −10
Original line number Diff line number Diff line
@@ -472,18 +472,17 @@ bool radeon_card_posted(struct radeon_device *rdev) 
		return false;



	/* first check CRTCs */

	if (ASIC_IS_DCE41(rdev)) {

	if (ASIC_IS_DCE4(rdev)) {

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

		if (reg & EVERGREEN_CRTC_MASTER_EN)

			return true;

	} else if (ASIC_IS_DCE4(rdev)) {

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

			if (rdev->num_crtc >= 4) {

				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

			}

			if (rdev->num_crtc >= 6) {

				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

			}

		if (reg & EVERGREEN_CRTC_MASTER_EN)

			return true;

	} else if (ASIC_IS_AVIVO(rdev)) {