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Commit 083f9560 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: print computed bpp in dp link configuration 



Pretty useful to debug our DP bandwidth woes.

v2: Also print out the required and available link bandwidth,
suggested by Chris Wilson.

v3: Also print out the input parameters so that diagnosing failures to
find a valid dp link configuration is possible.

v4: s/Display port/DP/ to shorten the output.

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5bc69bf9

drivers/gpu/drm/i915/intel_dp.c

+12 −6
Original line number Original line Diff line number Diff line
@@ -688,7 +688,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 
	int lane_count, clock;

	int lane_count, clock;

	int max_lane_count = intel_dp_max_lane_count(intel_dp);

	int max_lane_count = intel_dp_max_lane_count(intel_dp);

	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;

	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;

	int bpp;

	int bpp, mode_rate;

	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };

	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };





	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {

	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
@@ -702,24 +702,30 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 
		mode->clock = intel_dp->panel_fixed_mode->clock;

		mode->clock = intel_dp->panel_fixed_mode->clock;

	}

	}





	DRM_DEBUG_KMS("DP link computation with max lane count %i "

		      "max bw %02x pixel clock %iKHz\n",

		      max_lane_count, bws[max_clock], mode->clock);



	if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))

	if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))

		return false;

		return false;





	bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;

	bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;

	mode_rate = intel_dp_link_required(mode->clock, bpp);





	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {

	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {

		for (clock = 0; clock <= max_clock; clock++) {

		for (clock = 0; clock <= max_clock; clock++) {

			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);

			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);





			if (intel_dp_link_required(mode->clock, bpp)

			if (mode_rate <= link_avail) {

					<= link_avail) {

				intel_dp->link_bw = bws[clock];

				intel_dp->link_bw = bws[clock];

				intel_dp->lane_count = lane_count;

				intel_dp->lane_count = lane_count;

				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);

				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);

				DRM_DEBUG_KMS("Display port link bw %02x lane "

				DRM_DEBUG_KMS("DP link bw %02x lane "

						"count %d clock %d\n",

						"count %d clock %d bpp %d\n",

				       intel_dp->link_bw, intel_dp->lane_count,

				       intel_dp->link_bw, intel_dp->lane_count,

				       adjusted_mode->clock);

				       adjusted_mode->clock, bpp);

				DRM_DEBUG_KMS("DP link bw required %i available %i\n",

					      mode_rate, link_avail);

				return true;

				return true;

			}

			}

		}

		}