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Commit 074dff9a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "mmc: sdhci-msm: use max discard size supported for mmc queue"

parents 0a0170d1 6cf0c38f

drivers/mmc/core/core.c

+2 −1
Original line number Diff line number Diff line
@@ -3449,7 +3449,8 @@ unsigned int mmc_calc_max_discard(struct mmc_card *card) 
	struct mmc_host *host = card->host;

	unsigned int max_discard, max_trim;



	if (!host->max_busy_timeout)

	if (!host->max_busy_timeout ||

			(host->caps2 & MMC_CAP2_MAX_DISCARD_SIZE))

		return UINT_MAX;



	/*

drivers/mmc/host/sdhci-msm.c

+1 −1
Original line number Diff line number Diff line
@@ -4003,7 +4003,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
	host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;

	host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;

	host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK;

	host->quirks2 |= SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE;

	host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD;

	host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE;

	host->quirks2 |= SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT;
@@ -4066,6 +4065,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
	msm_host->mmc->caps2 |= MMC_CAP2_HS400_POST_TUNING;

	msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE;

	msm_host->mmc->caps2 |= MMC_CAP2_SANITIZE;

	msm_host->mmc->caps2 |= MMC_CAP2_MAX_DISCARD_SIZE;



	if (msm_host->pdata->nonremovable)

		msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE;

drivers/mmc/host/sdhci.c

+0 −4
Original line number Diff line number Diff line
@@ -3861,10 +3861,6 @@ int sdhci_add_host(struct sdhci_host *host) 
	if (override_timeout_clk)

		host->timeout_clk = override_timeout_clk;





	if (!(host->quirks2 & SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE))

		mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;



	mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;

	mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;

include/linux/mmc/host.h

+2 −0
Original line number Diff line number Diff line
@@ -436,6 +436,8 @@ struct mmc_host { 
#define MMC_CAP2_CMD_QUEUE	(1 << 26)	/* support eMMC command queue */

#define MMC_CAP2_SANITIZE       (1 << 27)               /* Support Sanitize */

#define MMC_CAP2_SLEEP_AWAKE	(1 << 28)	/* Use Sleep/Awake (CMD5) */

/* use max discard ignoring max_busy_timeout parameter */

#define MMC_CAP2_MAX_DISCARD_SIZE	(1 << 29)



	mmc_pm_flag_t		pm_caps;	/* supported pm features */

include/linux/mmc/sdhci.h

+10 −16
Original line number Diff line number Diff line
@@ -129,31 +129,25 @@ struct sdhci_host { 
 * required frequency.

 */

#define SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK		(1<<11)

/*

 * Dont use the max_discard_to in sdhci driver so that the maximum discard

 * unit gets picked by the mmc queue. Otherwise, it takes a long time for

 * secure discard kind of operations to complete.

 */

#define SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE		(1<<12)

/*

 * Ignore data timeout error for R1B commands as there will be no

 * data associated and the busy timeout value for these commands

 * could be lager than the maximum timeout value that controller

 * can handle.

 */

#define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD		(1<<13)

#define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD		(1<<12)

/*

 * The preset value registers are not properly initialized by

 * some hardware and hence preset value must not be enabled for

 * such controllers.

 */

#define SDHCI_QUIRK2_BROKEN_PRESET_VALUE		(1<<14)

#define SDHCI_QUIRK2_BROKEN_PRESET_VALUE		(1<<13)

/*

 * Some controllers define the usage of 0xF in data timeout counter

 * register (0x2E) which is actually a reserved bit as per

 * specification.

 */

#define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT		(1<<15)

#define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT		(1<<14)

/*

 * This is applicable for controllers that advertize timeout clock

 * value in capabilities register (bit 5-0) as just 50MHz whereas the
@@ -166,27 +160,27 @@ struct sdhci_host { 
 * will be used in such cases to avoid controller mulplication when timeout is

 * calculated based on the base clock.

 */

#define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4			(1<<16)

#define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4			(1<<15)

/*

 * Some SDHC controllers are unable to handle data-end bit error in

 * 1-bit mode of SDIO.

 */

#define SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR             (1<<17)

#define SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR             (1<<16)



/*

 * Some SDHC controllers do not require data buffers alignment, skip

 * the bounce buffer logic when preparing data

 */

#define SDHCI_QUIRK2_ADMA_SKIP_DATA_ALIGNMENT		(1<<18)

#define SDHCI_QUIRK2_ADMA_SKIP_DATA_ALIGNMENT		(1<<17)



/* Controller has nonstandard clock management */

#define SDHCI_QUIRK_NONSTANDARD_CLOCK			(1<<19)

#define SDHCI_QUIRK_NONSTANDARD_CLOCK			(1<<18)

/* Capability register bit-63 indicates HS400 support */

#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<20)

#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<19)

/* Use reset workaround in case sdhci reset timeouts */

#define SDHCI_QUIRK2_USE_RESET_WORKAROUND		(1<<21)

#define SDHCI_QUIRK2_USE_RESET_WORKAROUND		(1<<20)

/* Some controllers doesn't have have any LED control */

#define SDHCI_QUIRK2_BROKEN_LED_CONTROL			(1<<22)

#define SDHCI_QUIRK2_BROKEN_LED_CONTROL			(1<<21)



	int irq;		/* Device IRQ */

	void __iomem *ioaddr;	/* Mapped address */