Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 066941bd authored by H. Peter Anvin's avatar H. Peter Anvin Committed by Ingo Molnar
Browse files

x86: unmask CPUID levels on Intel CPUs 



Impact: Fixes crashes with misconfigured BIOSes on XSAVE hardware

Avuton Olrich reported early boot crashes with v2.6.28 and
bisected it down to dc1e35c6
("x86, xsave: enable xsave/xrstor on cpus with xsave support").

If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available.  This is required for some
features to work, in particular XSAVE.

Reported-and-bisected-by: default avatarAvuton Olrich <avuton@gmail.com>
Tested-by: default avatarAvuton Olrich <avuton@gmail.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent bdf21a49

arch/x86/kernel/cpu/intel.c

+10 −0
Original line number Diff line number Diff line
@@ -29,6 +29,16 @@ 


static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)

{

	u64 misc_enable;



	/* Unmask CPUID levels if masked */

	if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&

	    (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {

		misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;

		wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		c->cpuid_level = cpuid_eax(0);

	}



	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||

		(c->x86 == 0x6 && c->x86_model >= 0x0e))

		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);