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Commit 05e1ec9d authored by Sahitya Tummala's avatar Sahitya Tummala
Browse files

ARM: dts: msm: Add SDHC1 support for msmtitanium 



Add pinctrl and sdhc1 device entries to enable eMMC.

Change-Id: Id3d3fb35f7de097cc29e9024118d5fd232b2b05c
Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
parent 2be5ff68

arch/arm/boot/dts/qcom/msmtitanium-cdp.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -22,3 +22,27 @@ 
	pinctrl-0 = <&uart_console_active>;

};



&sdhc_1 {

	/* device core power supply */

	vdd-supply = <&pmtitanium_l8>;

	qcom,vdd-voltage-level = <2900000 2900000>;

	qcom,vdd-current-level = <200 570000>;



	/* device communication power supply */

	vdd-io-supply = <&pmtitanium_l5>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <200 325000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on  &sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000

								384000000>;

	qcom,nonremovable;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";



	status = "ok";

};

arch/arm/boot/dts/qcom/msmtitanium-mtp.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -22,3 +22,27 @@ 
	pinctrl-0 = <&uart_console_active>;

};



&sdhc_1 {

	/* device core power supply */

	vdd-supply = <&pmtitanium_l8>;

	qcom,vdd-voltage-level = <2900000 2900000>;

	qcom,vdd-current-level = <200 570000>;



	/* device communication power supply */

	vdd-io-supply = <&pmtitanium_l5>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <200 325000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on  &sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000

								384000000>;

	qcom,nonremovable;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";



	status = "ok";

};

arch/arm/boot/dts/qcom/msmtitanium-pinctrl.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -126,6 +126,20 @@ 
			};

		};



		sdc1_rclk_on: sdc1_rclk_on {

			config {

				pins = "sdc1_rclk";

				bias-pull-down; /* pull down */

			};

		};



		sdc1_rclk_off: sdc1_rclk_off {

			config {

				pins = "sdc1_rclk";

				bias-pull-down; /* pull down */

			};

		};



		i2c_2 {

			i2c_2_active: i2c_2_active {

				/* active state */

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+17 −6
Original line number Diff line number Diff line
@@ -1025,17 +1025,23 @@ 


	sdhc_1: sdhci@7824900 {

		compatible = "qcom,sdhci-msm";

		reg = <0x7824900 0x500>, <0x7824000 0x800>;

		reg-names = "hc_mem", "core_mem";

		reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>;

		reg-names = "hc_mem", "core_mem", "cmdq_mem";



		interrupts = <0 123 0>, <0 138 0>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,bus-width = <8>;



		qcom,devfreq,freq-table = <52000000 200000000>;

		qcom,devfreq,freq-table = <50000000 200000000>;



		qcom,cpu-dma-latency-us = <60 340 900>;

		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <2 200>;



		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cmdq-latency-us = <2 200>, <2 200>;



		qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;



		qcom,msm-bus,name = "sdhc1";

		qcom,msm-bus,num-cases = <9>;
@@ -1053,8 +1059,13 @@ 
			100000000 200000000 400000000 4294967295>;



		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>;

		clock-names = "iface_clk", "core_clk";

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>,

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk";

		qcom,ice-clk-rates = <270000000 160000000>;

		qcom,large-address-bus;



		status = "disabled";

	};



	spmi_bus: qcom,spmi@200f000 {