Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

  External caches (if present) must be configured and disabled.

- Architected timers

  CNTFRQ must be programmed with the timer frequency.

  If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)

  set where available.

  CNTFRQ must be programmed with the timer frequency and CNTVOFF must

  be programmed with a consistent value on all CPUs.  If entering the

  kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where

  available.

- Coherency

  All CPUs to be booted by the kernel must be part of the same coherency

  the kernel image will be entered must be initialised by software at a

  higher exception level to prevent execution in an UNKNOWN state.

The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.

The boot loader is expected to enter the kernel on each CPU in the

following manner:

- The primary CPU must jump directly to the first instruction of the

  kernel image.  The device tree blob passed by this CPU must contain

  for each CPU node:

    1. An 'enable-method' property. Currently, the only supported value

       for this field is the string "spin-table".

    2. A 'cpu-release-addr' property identifying a 64-bit,

       zero-initialised memory location.

  an 'enable-method' property for each cpu node.  The supported

  enable-methods are described below.

  It is expected that the bootloader will generate these device tree

  properties and insert them into the blob prior to kernel entry.

- Any secondary CPUs must spin outside of the kernel in a reserved area

  of memory (communicated to the kernel by a /memreserve/ region in the

- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'

  property in their cpu node.  This property identifies a

  naturally-aligned 64-bit zero-initalised memory location.

  These CPUs should spin outside of the kernel in a reserved area of

  memory (communicated to the kernel by a /memreserve/ region in the

  device tree) polling their cpu-release-addr location, which must be

  contained in the reserved region.  A wfe instruction may be inserted

  to reduce the overhead of the busy-loop and a sev will be issued by

  the primary CPU.  When a read of the location pointed to by the

  cpu-release-addr returns a non-zero value, the CPU must jump directly

  to this value.

  cpu-release-addr returns a non-zero value, the CPU must jump to this

  value.  The value will be written as a single 64-bit little-endian

  value, so CPUs must convert the read value to their native endianness

  before jumping to it.

- CPUs with a "psci" enable method should remain outside of

  the kernel (i.e. outside of the regions of memory described to the

  kernel in the memory node, or in a reserved area of memory described

  to the kernel by a /memreserve/ region in the device tree).  The

  kernel will issue CPU_ON calls as described in ARM document number ARM

  DEN 0022A ("Power State Coordination Interface System Software on ARM

  processors") to bring CPUs into the kernel.

  The device tree should contain a 'psci' node, as described in

  Documentation/devicetree/bindings/arm/psci.txt.

- Secondary CPU general-purpose register settings

  x0 = 0 (reserved for future use)

TTBR0.

AArch64 Linux memory layout:

AArch64 Linux memory layout with 4KB pages:

Start			End			Size		Use

-----------------------------------------------------------------------

ffffffbffbe00000	ffffffbffbe0ffff	  64KB		PCI I/O space

ffffffbbffff0000	ffffffbcffffffff	  ~2MB		[guard]

ffffffbffbe10000	ffffffbcffffffff	  ~2MB		[guard]

ffffffbffc000000	ffffffbfffffffff	  64MB		modules

ffffffc000000000	ffffffffffffffff	 256GB		kernel logical memory map

AArch64 Linux memory layout with 64KB pages:

Start			End			Size		Use

-----------------------------------------------------------------------

0000000000000000	000003ffffffffff	   4TB		user

fffffc0000000000	fffffdfbfffeffff	  ~2TB		vmalloc

fffffdfbffff0000	fffffdfbffffffff	  64KB		[guard page]

fffffdfc00000000	fffffdfdffffffff	   8GB		vmemmap

fffffdfe00000000	fffffdfffbbfffff	  ~8GB		[guard, future vmmemap]

fffffdfffbc00000	fffffdfffbdfffff	   2MB		earlyprintk device

fffffdfffbe00000	fffffdfffbe0ffff	  64KB		PCI I/O space

fffffdfffbe10000	fffffdfffbffffff	  ~2MB		[guard]

fffffdfffc000000	fffffdffffffffff	  64MB		modules

fffffe0000000000	ffffffffffffffff	   2TB		kernel logical memory map

Translation table lookup with 4KB pages:

+--------+--------+--------+--------+--------+--------+--------+--------+

config ARM64

	def_bool y

	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE

	select ARCH_USE_CMPXCHG_LOCKREF

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION

	select ARCH_WANT_FRAME_POINTERS

config TRACE_IRQFLAGS_SUPPORT

	def_bool y

config GENERIC_LOCKBREAK

	def_bool y

	depends on SMP && PREEMPT

config RWSEM_GENERIC_SPINLOCK

	def_bool y

	  look-up. AArch32 emulation is not available when this feature

	  is enabled.

config CPU_BIG_ENDIAN

       bool "Build big-endian kernel"

       help

         Say Y if you plan on running a kernel in big-endian mode.

config SMP

	bool "Symmetric Multi-Processing"

	select USE_GENERIC_SMP_HELPERS

	default "8" if ARCH_XGENE

	default "4"

config HOTPLUG_CPU

	bool "Support for hot-pluggable CPUs"

	depends on SMP

	help

	  Say Y here to experiment with turning CPUs off and on.  CPUs

	  can be controlled through /sys/devices/system/cpu.

source kernel/Kconfig.preempt

config HZ

KBUILD_DEFCONFIG := defconfig

KBUILD_CFLAGS	+= -mgeneral-regs-only

ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)

KBUILD_CPPFLAGS	+= -mbig-endian

AS		+= -EB

LD		+= -EB

else

KBUILD_CPPFLAGS	+= -mlittle-endian

AS		+= -EL

LD		+= -EL

endif

comma = ,

CONFIG_ARCH_VEXPRESS=y

CONFIG_ARCH_XGENE=y

CONFIG_SMP=y

CONFIG_PREEMPT_VOLUNTARY=y

CONFIG_PREEMPT=y

CONFIG_CMDLINE="console=ttyAMA0"

# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

CONFIG_COMPAT=y