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Commit 059c7634 authored by Matt Wagantall's avatar Matt Wagantall
Browse files

Merge tag 'v3.18.13' into msm-3.18 



Linux 3.18.13

Resolve trivial context conflicts as part of the merge.

Conflicts:
	arch/arm64/include/asm/cpufeature.h
	arch/arm64/include/asm/io.h
	arch/arm64/kernel/cpuinfo.c
	arch/arm64/kernel/setup.c

Change-Id: I483193553f4eea677865c9d5f8c46bd53b906e27
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parents eb9dfeb4 72d391fe

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 18

SUBLEVEL = 12

SUBLEVEL = 13

EXTRAVERSION =

NAME = Shuffling Zombie Juror

arch/arc/kernel/signal.c

+18 −6
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ stash_usr_regs(struct rt_sigframe __user *sf, struct pt_regs *regs, 
	       sigset_t *set)

{

	int err;

	err = __copy_to_user(&(sf->uc.uc_mcontext.regs), regs,

	err = __copy_to_user(&(sf->uc.uc_mcontext.regs.scratch), regs,

			     sizeof(sf->uc.uc_mcontext.regs.scratch));

	err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(sigset_t));
@@ -83,7 +83,7 @@ static int restore_usr_regs(struct pt_regs *regs, struct rt_sigframe __user *sf) 
	if (!err)

		set_current_blocked(&set);



	err |= __copy_from_user(regs, &(sf->uc.uc_mcontext.regs),

	err |= __copy_from_user(regs, &(sf->uc.uc_mcontext.regs.scratch),

				sizeof(sf->uc.uc_mcontext.regs.scratch));



	return err;
@@ -131,6 +131,15 @@ SYSCALL_DEFINE0(rt_sigreturn) 
	/* Don't restart from sigreturn */

	syscall_wont_restart(regs);



	/*

	 * Ensure that sigreturn always returns to user mode (in case the

	 * regs saved on user stack got fudged between save and sigreturn)

	 * Otherwise it is easy to panic the kernel with a custom

	 * signal handler and/or restorer which clobberes the status32/ret

	 * to return to a bogus location in kernel mode.

	 */

	regs->status32 |= STATUS_U_MASK;



	return regs->r0;



badframe:
@@ -229,8 +238,11 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) 


	/*

	 * handler returns using sigreturn stub provided already by userpsace

	 * If not, nuke the process right away

	 */

	BUG_ON(!(ksig->ka.sa.sa_flags & SA_RESTORER));

	if(!(ksig->ka.sa.sa_flags & SA_RESTORER))

		return 1;



	regs->blink = (unsigned long)ksig->ka.sa.sa_restorer;



	/* User Stack for signal handler will be above the frame just carved */
@@ -296,12 +308,12 @@ static void 
handle_signal(struct ksignal *ksig, struct pt_regs *regs)

{

	sigset_t *oldset = sigmask_to_save();

	int ret;

	int failed;



	/* Set up the stack frame */

	ret = setup_rt_frame(ksig, oldset, regs);

	failed = setup_rt_frame(ksig, oldset, regs);



	signal_setup_done(ret, ksig, 0);

	signal_setup_done(failed, ksig, 0);

}



void do_signal(struct pt_regs *regs)

arch/arm/mach-sunxi/Kconfig

+2 −4
Original line number Diff line number Diff line 
menuconfig ARCH_SUNXI

	bool "Allwinner SoCs" if ARCH_MULTI_V7

	select ARCH_REQUIRE_GPIOLIB

	select ARCH_HAS_RESET_CONTROLLER

	select CLKSRC_MMIO

	select GENERIC_IRQ_CHIP

	select PINCTRL

	select SUN4I_TIMER

	select RESET_CONTROLLER



if ARCH_SUNXI
@@ -20,10 +22,8 @@ config MACH_SUN5I 
config MACH_SUN6I

	bool "Allwinner A31 (sun6i) SoCs support"

	default ARCH_SUNXI

	select ARCH_HAS_RESET_CONTROLLER

	select ARM_GIC

	select MFD_SUN6I_PRCM

	select RESET_CONTROLLER

	select SUN5I_HSTIMER



config MACH_SUN7I
@@ -37,9 +37,7 @@ config MACH_SUN7I 
config MACH_SUN8I

	bool "Allwinner A23 (sun8i) SoCs support"

	default ARCH_SUNXI

	select ARCH_HAS_RESET_CONTROLLER

	select ARM_GIC

	select MFD_SUN6I_PRCM

	select RESET_CONTROLLER



endif

arch/arm64/Kconfig

+129 −0
Original line number Diff line number Diff line
@@ -286,6 +286,135 @@ endmenu 


menu "Kernel Features"



menu "ARM errata workarounds via the alternatives framework"



config ARM64_ERRATUM_826319

	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or

	  AXI master interface and an L2 cache.



	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors

	  and is unable to accept a certain write via this interface, it will

	  not progress on read data presented on the read data channel and the

	  system can deadlock.



	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



config ARM64_ERRATUM_827319

	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI

	  master interface and an L2 cache.



	  Under certain conditions this erratum can cause a clean line eviction

	  to occur at the same time as another transaction to the same address

	  on the AMBA 5 CHI interface, which can cause data corruption if the

	  interconnect reorders the two transactions.



	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



config ARM64_ERRATUM_824069

	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected

	  to a coherent interconnect.



	  If a Cortex-A53 processor is executing a store or prefetch for

	  write instruction at the same time as a processor in another

	  cluster is executing a cache maintenance operation to the same

	  address, then this erratum might cause a clean cache line to be

	  incorrectly marked as dirty.



	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this option does not necessarily enable the

	  workaround, as it depends on the alternative framework, which will

	  only patch the kernel if an affected CPU is detected.



	  If unsure, say Y.



config ARM64_ERRATUM_819472

	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache

	  present when it is connected to a coherent interconnect.



	  If the processor is executing a load and store exclusive sequence at

	  the same time as a processor in another cluster is executing a cache

	  maintenance operation to the same address, then this erratum might

	  cause data corruption.



	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



config ARM64_ERRATUM_832075

	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 832075 on Cortex-A57 parts up to r1p2.



	  Affected Cortex-A57 parts might deadlock when exclusive load/store

	  instructions to Write-Back memory are mixed with Device loads.



	  The workaround is to promote device loads to use Load-Acquire

	  semantics.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



config ARM64_ERRATUM_845719

	bool "Cortex-A53: 845719: a load might read incorrect data"

	depends on COMPAT

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 845719 on Cortex-A53 parts up to r0p4.



	  When running a compat (AArch32) userspace on an affected Cortex-A53

	  part, a load at EL0 from a virtual address that matches the bottom 32

	  bits of the virtual address used by a recent load at (AArch64) EL1

	  might return incorrect data.



	  The workaround is to write the contextidr_el1 register on exception

	  return to a 32-bit task.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



endmenu





choice

	prompt "Page size"

	default ARM64_4K_PAGES

arch/arm64/include/asm/alternative-asm.h

0 → 100644
+29 −0
Original line number Diff line number Diff line 
#ifndef __ASM_ALTERNATIVE_ASM_H

#define __ASM_ALTERNATIVE_ASM_H



#ifdef __ASSEMBLY__



.macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len

	.word \orig_offset - .

	.word \alt_offset - .

	.hword \feature

	.byte \orig_len

	.byte \alt_len

.endm



.macro alternative_insn insn1 insn2 cap

661:	\insn1

662:	.pushsection .altinstructions, "a"

	altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f

	.popsection

	.pushsection .altinstr_replacement, "ax"

663:	\insn2

664:	.popsection

	.if ((664b-663b) != (662b-661b))

		.error "Alternatives instruction length mismatch"

	.endif

.endm



#endif  /*  __ASSEMBLY__  */



#endif /* __ASM_ALTERNATIVE_ASM_H */