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Commit 055a4e1c authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add missing ahb clock to ispif for msm8937"

parents 13918751 4e7bd925

arch/arm/boot/dts/qcom/msm8937-camera.dtsi

+16 −10
Original line number Diff line number Diff line
@@ -153,8 +153,10 @@ 
		qcom,num-isps = <0x2>;

		vfe0_vdd_supply = <&gdsc_vfe>;

		vfe1_vdd_supply = <&gdsc_vfe1>;

		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,

			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

		clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

			<&clock_gcc clk_gcc_camss_ahb_clk>,

			<&clock_gcc clk_gcc_camss_top_ahb_clk>,

			<&clock_gcc clk_camss_top_ahb_clk_src>,

			<&clock_gcc clk_csi0_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0_clk>,

			<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
@@ -173,7 +175,9 @@ 
			<&clock_gcc clk_vfe1_clk_src>,

			<&clock_gcc clk_gcc_camss_vfe1_clk>,

			<&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

		clock-names = "ispif_ahb_clk",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"camss_ahb_src",

			"csi0_src_clk", "csi0_clk",

			"csi0_rdi_clk", "csi0_pix_clk",

			"csi1_src_clk", "csi1_clk",
@@ -183,18 +187,20 @@ 
			"vfe0_clk_src", "camss_vfe_vfe0_clk",

			"camss_csi_vfe0_clk", "vfe1_clk_src",

			"camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";

		qcom,clock-rates = <0 61540000

		qcom,clock-rates = <61540000 0 0 0

			200000000 0 0 0

			200000000 0 0 0

			200000000 0 0 0

			0 0 0

			0 0 0>;

		qcom,clock-control = "NO_SET_RATE", "SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";

		qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE", "SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE";

	};



	vfe0: qcom,vfe0@1b10000 {

arch/arm/boot/dts/qcom/msmgold-camera.dtsi

+16 −10
Original line number Diff line number Diff line
@@ -153,8 +153,10 @@ 
		qcom,num-isps = <0x2>;

		vfe0_vdd_supply = <&gdsc_vfe>;

		vfe1_vdd_supply = <&gdsc_vfe1>;

		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,

			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

		clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

			<&clock_gcc clk_gcc_camss_ahb_clk>,

			<&clock_gcc clk_gcc_camss_top_ahb_clk>,

			<&clock_gcc clk_camss_top_ahb_clk_src>,

			<&clock_gcc clk_csi0_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0_clk>,

			<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
@@ -173,7 +175,9 @@ 
			<&clock_gcc clk_vfe1_clk_src>,

			<&clock_gcc clk_gcc_camss_vfe1_clk>,

			<&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

		clock-names = "ispif_ahb_clk",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"camss_ahb_src",

			"csi0_src_clk", "csi0_clk",

			"csi0_rdi_clk", "csi0_pix_clk",

			"csi1_src_clk", "csi1_clk",
@@ -183,18 +187,20 @@ 
			"vfe0_clk_src", "camss_vfe_vfe0_clk",

			"camss_csi_vfe0_clk", "vfe1_clk_src",

			"camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";

		qcom,clock-rates = <0 61540000

		qcom,clock-rates = <61540000 0 0 0

			200000000 0 0 0

			200000000 0 0 0

			200000000 0 0 0

			0 0 0

			0 0 0>;

		qcom,clock-control = "NO_SET_RATE", "SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";

		qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE", "SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE";

	};



	vfe0: qcom,vfe0@1b10000 {

arch/arm/boot/dts/qcom/msmtitanium-camera.dtsi

+16 −10
Original line number Diff line number Diff line
@@ -176,8 +176,10 @@ 
		qcom,num-isps = <0x2>;

		vfe0_vdd_supply = <&gdsc_vfe>;

		vfe1_vdd_supply = <&gdsc_vfe1>;

		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,

			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

		clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

			<&clock_gcc clk_gcc_camss_ahb_clk>,

			<&clock_gcc clk_gcc_camss_top_ahb_clk>,

			<&clock_gcc clk_camss_top_ahb_clk_src>,

			<&clock_gcc clk_csi0_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0_clk>,

			<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
@@ -196,7 +198,9 @@ 
			<&clock_gcc clk_vfe1_clk_src>,

			<&clock_gcc clk_gcc_camss_vfe1_clk>,

			<&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

		clock-names = "ispif_ahb_clk",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"camss_ahb_src",

			"csi0_src_clk", "csi0_clk",

			"csi0_rdi_clk", "csi0_pix_clk",

			"csi1_src_clk", "csi1_clk",
@@ -206,18 +210,20 @@ 
			"vfe0_clk_src", "camss_vfe_vfe0_clk",

			"camss_csi_vfe0_clk", "vfe1_clk_src",

			"camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";

		qcom,clock-rates = <0 61540000

		qcom,clock-rates = <61540000 0 0 0

			200000000 0 0 0

			200000000 0 0 0

			200000000 0 0 0

			0 0 0

			0 0 0>;

		qcom,clock-control = "NO_SET_RATE", "SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";

		qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE", "SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE";

	};



	vfe0: qcom,vfe0@1b10000 {