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Commit 05413245 authored by Tang Yuantian's avatar Tang Yuantian Committed by Kumar Gala
Browse files

powerpc/85xx: Add p2020rdb-pc dts support 



Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarTang Yuantian <b29983@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 35ce1b5a

arch/powerpc/boot/dts/p2020rdb-pc.dtsi

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+241 −0
Original line number Diff line number Diff line 
/*

 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)

 *

 * Copyright 2011 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



&lbc {

	nor@0,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "cfi-flash";

		reg = <0x0 0x0 0x1000000>;

		bank-width = <2>;

		device-width = <1>;



		partition@0 {

			/* This location must not be altered  */

			/* 256KB for Vitesse 7385 Switch firmware */

			reg = <0x0 0x00040000>;

			label = "NOR Vitesse-7385 Firmware";

			read-only;

		};



		partition@40000 {

			/* 256KB for DTB Image */

			reg = <0x00040000 0x00040000>;

			label = "NOR DTB Image";

		};



		partition@80000 {

			/* 3.5 MB for Linux Kernel Image */

			reg = <0x00080000 0x00380000>;

			label = "NOR Linux Kernel Image";

		};



		partition@400000 {

			/* 11MB for JFFS2 based Root file System */

			reg = <0x00400000 0x00b00000>;

			label = "NOR JFFS2 Root File System";

		};



		partition@f00000 {

			/* This location must not be altered  */

			/* 512KB for u-boot Bootloader Image */

			/* 512KB for u-boot Environment Variables */

			reg = <0x00f00000 0x00100000>;

			label = "NOR U-Boot Image";

			read-only;

		};

	};



	nand@1,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "fsl,p2020-fcm-nand",

				 "fsl,elbc-fcm-nand";

		reg = <0x1 0x0 0x40000>;



		partition@0 {

			/* This location must not be altered  */

			/* 1MB for u-boot Bootloader Image */

			reg = <0x0 0x00100000>;

			label = "NAND U-Boot Image";

			read-only;

		};



		partition@100000 {

			/* 1MB for DTB Image */

			reg = <0x00100000 0x00100000>;

			label = "NAND DTB Image";

		};



		partition@200000 {

			/* 4MB for Linux Kernel Image */

			reg = <0x00200000 0x00400000>;

			label = "NAND Linux Kernel Image";

		};



		partition@600000 {

			/* 4MB for Compressed Root file System Image */

			reg = <0x00600000 0x00400000>;

			label = "NAND Compressed RFS Image";

		};



		partition@a00000 {

			/* 7MB for JFFS2 based Root file System */

			reg = <0x00a00000 0x00700000>;

			label = "NAND JFFS2 Root File System";

		};



		partition@1100000 {

			/* 15MB for JFFS2 based Root file System */

			reg = <0x01100000 0x00f00000>;

			label = "NAND Writable User area";

		};

	};



	L2switch@2,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "vitesse-7385";

		reg = <0x2 0x0 0x20000>;

	};



	cpld@3,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "cpld";

		reg = <0x3 0x0 0x20000>;

		read-only;

	};

};



&soc {

	i2c@3000 {

		rtc@68 {

			compatible = "pericom,pt7c4338";

			reg = <0x68>;

		};

	};



	spi@7000 {

		flash@0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "spansion,m25p80";

			reg = <0>;

			spi-max-frequency = <40000000>;



			partition@0 {

				/* 512KB for u-boot Bootloader Image */

				reg = <0x0 0x00080000>;

				label = "SPI U-Boot Image";

				read-only;

			};



			partition@80000 {

				/* 512KB for DTB Image */

				reg = <0x00080000 0x00080000>;

				label = "SPI DTB Image";

			};



			partition@100000 {

				/* 4MB for Linux Kernel Image */

				reg = <0x00100000 0x00400000>;

				label = "SPI Linux Kernel Image";

			};



			partition@500000 {

				/* 4MB for Compressed RFS Image */

				reg = <0x00500000 0x00400000>;

				label = "SPI Compressed RFS Image";

			};



			partition@900000 {

				/* 7MB for JFFS2 based RFS */

				reg = <0x00900000 0x00700000>;

				label = "SPI JFFS2 RFS";

			};

		};

	};



	usb@22000 {

		phy_type = "ulpi";

	};



	mdio@24520 {

		phy0: ethernet-phy@0 {

			interrupts = <3 1 0 0>;

			reg = <0x0>;

			};

		phy1: ethernet-phy@1 {

			interrupts = <2 1 0 0>;

			reg = <0x1>;

			};

	};



	mdio@25520 {

		tbi0: tbi-phy@11 {

			reg = <0x11>;

			device_type = "tbi-phy";

		};

	};



	mdio@26520 {

		status = "disabled";

	};



	ptp_clock@24e00 {

		fsl,tclk-period = <5>;

		fsl,tmr-prsc = <200>;

		fsl,tmr-add = <0xCCCCCCCD>;

		fsl,tmr-fiper1 = <0x3B9AC9FB>;

		fsl,tmr-fiper2 = <0x0001869B>;

		fsl,max-adj = <249999999>;

	};



	enet0: ethernet@24000 {

		fixed-link = <1 1 1000 0 0>;

		phy-connection-type = "rgmii-id";

	};



	enet1: ethernet@25000 {

		tbi-handle = <&tbi0>;

		phy-handle = <&phy0>;

		phy-connection-type = "sgmii";

	};



	enet2: ethernet@26000 {

		phy-handle = <&phy1>;

		phy-connection-type = "rgmii-id";

	};

};

arch/powerpc/boot/dts/p2020rdb-pc_32b.dts

0 → 100644
+96 −0
Original line number Diff line number Diff line 
/*

 * P2020 RDB-PC 32Bit Physical Address Map Device Tree Source

 *

 * Copyright 2011 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/include/ "fsl/p2020si-pre.dtsi"



/ {

	model = "fsl,P2020RDB";

	compatible = "fsl,P2020RDB-PC";



	memory {

		device_type = "memory";

	};



	lbc: localbus@ffe05000 {

		reg = <0 0xffe05000 0 0x1000>;



		/* NOR and NAND Flashes */

		ranges = <0x0 0x0 0x0 0xef000000 0x01000000

			  0x1 0x0 0x0 0xff800000 0x00040000

			  0x2 0x0 0x0 0xffb00000 0x00020000

			  0x3 0x0 0x0 0xffa00000 0x00020000>;

	};



	soc: soc@ffe00000 {

		ranges = <0x0 0x0 0xffe00000 0x100000>;

	};



	pci0: pcie@ffe08000 {

		reg = <0 0xffe08000 0 0x1000>;

		status = "disabled";

	};



	pci1: pcie@ffe09000 {

		reg = <0 0xffe09000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0xe0000000

				  0x2000000 0x0 0xe0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};



	pci2: pcie@ffe0a000 {

		reg = <0 0xffe0a000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0xe0000000

				  0x2000000 0x0 0xe0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};

};



/include/ "p2020rdb-pc.dtsi"

/include/ "fsl/p2020si-post.dtsi"

arch/powerpc/boot/dts/p2020rdb-pc_36b.dts

0 → 100644
+96 −0
Original line number Diff line number Diff line 
/*

 * P2020 RDB-PC 36Bit Physical Address Map Device Tree Source

 *

 * Copyright 2011 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/include/ "fsl/p2020si-pre.dtsi"



/ {

	model = "fsl,P2020RDB";

	compatible = "fsl,P2020RDB-PC";



	memory {

		device_type = "memory";

	};



	lbc: localbus@fffe05000 {

		reg = <0xf 0xffe05000 0 0x1000>;



		/* NOR and NAND Flashes */

		ranges = <0x0 0x0 0xf 0xef000000 0x01000000

			  0x1 0x0 0xf 0xff800000 0x00040000

			  0x2 0x0 0xf 0xffb00000 0x00020000

			  0x3 0x0 0xf 0xffa00000 0x00020000>;

	};



	soc: soc@fffe00000 {

		ranges = <0x0 0xf 0xffe00000 0x100000>;

	};



	pci0: pcie@fffe08000 {

		reg = <0xf 0xffe08000 0 0x1000>;

		status = "disabled";

	};



	pci1: pcie@fffe09000 {

		reg = <0xf 0xffe09000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0xe0000000

				  0x2000000 0x0 0xe0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};



	pci2: pcie@fffe0a000 {

		reg = <0xf 0xffe0a000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0xe0000000

				  0x2000000 0x0 0xe0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};

};



/include/ "p2020rdb-pc.dtsi"

/include/ "fsl/p2020si-post.dtsi"