Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0516e464 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
Browse files

[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data 



This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 855c551f

arch/arm/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -778,6 +778,18 @@ config ARM_ERRATA_458693 
	  in the ACTLR register. Note that setting specific bits in the ACTLR

	  register may not be available in non-secure mode.



config ARM_ERRATA_460075

	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"

	depends on CPU_V7

	help

	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)

	  erratum. Any asynchronous access to the L2 cache may encounter a

	  situation in which recent store transactions to the L2 cache are lost

	  and overwritten with stale memory contents from external memory. The

	  workaround disables the write-allocate mode for the L2 cache via the

	  ACTLR register. Note that setting specific bits in the ACTLR register

	  may not be available in non-secure mode.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/mm/proc-v7.S

+5 −0
Original line number Diff line number Diff line
@@ -193,6 +193,11 @@ __v7_setup: 
	orr	r10, r10, #(1 << 5)		@ set L1NEON to 1

	orr	r10, r10, #(1 << 9)		@ set PLDNOP to 1

	mcr	p15, 0, r10, c1, c0, 1		@ write aux control register

#endif

#ifdef CONFIG_ARM_ERRATA_460075

	mrc	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register

	orr	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit

	mcr	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register

#endif

	mov	r10, #0

#ifdef HARVARD_CACHE