Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 04b19d48 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-for-v3.16/fixes-not-urgent-signed' of...

Merge tag 'omap-for-v3.16/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

Merge "ARM: omap non urgent fixes for v3.16 merge window, resend" from Tony
Lindgren:

Non urgent omap fixes for v3.16 merge window.

* tag 'omap-for-v3.16/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
  ARM: dts: am335x-boneblack: remove use of ti,vcc-aux-disable-is-sleep
  ARM: OMAP2+: free use_gptimer_clksrc variable after boot
  ARM: OMAP5: Redo THUMB mode switch on secondary CPU
  ARM: dts: AM4372: add l3-noc information
  ARM: dts: DRA7: Use dra7-l3-noc instead of omap4-l3-noc

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 6580ad3f e610c9d3
Loading
Loading
Loading
Loading
+0 −1
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@
	pinctrl-0 = <&emmc_pins>;
	bus-width = <8>;
	status = "okay";
	ti,vcc-aux-disable-is-sleep;
};

&am33xx_pinmux {
+5 −1
Original line number Diff line number Diff line
@@ -67,11 +67,15 @@
	};

	ocp {
		compatible = "simple-bus";
		compatible = "ti,am4372-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";
		reg = <0x44000000 0x400000
		       0x44800000 0x400000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		prcm: prcm@44df0000 {
			compatible = "ti,am4-prcm";
+1 −1
Original line number Diff line number Diff line
@@ -341,7 +341,7 @@
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00800000 0x1F600000>;
			reg = <0x00a00000 0x1f600000>;
		};
	};
};
+3 −3
Original line number Diff line number Diff line
@@ -99,13 +99,13 @@
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		compatible = "ti,dra7-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2";
		reg = <0x44000000 0x2000>,
		      <0x44800000 0x3000>;
		reg = <0x44000000 0x1000000>,
		      <0x45000000 0x1000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

+1 −5
Original line number Diff line number Diff line
@@ -31,10 +31,6 @@
 * register AuxCoreBoot0.
 */
ENTRY(omap5_secondary_startup)
.arm
THUMB( adr     r9, BSYM(wait)  )       @ CPU may be entered in ARM mode.
THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
THUMB( .thumb                  )       @ switch to Thumb now.
wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
	ldr	r0, [r2]
	mov	r0, r0, lsr #5
@@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
	cmp	r0, r4
	bne	wait
	b	secondary_startup
END(omap5_secondary_startup)
ENDPROC(omap5_secondary_startup)
/*
 * OMAP4 specific entry point for secondary CPU to jump from ROM
 * code.  This routine also provides a holding flag into which
Loading