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Commit 045f0890 authored by Andre Przywara's avatar Andre Przywara Committed by Sasha Levin
Browse files

arm64: GICv3: introduce symbolic names for GICv3 ICC_SGI1R_EL1 fields 



[ Upstream commit 7e5802781c3e109558ddfd8b02155ad24d872ee7 ]

The gic_send_sgi() function used hardcoded bit shift values to
generate the ICC_SGI1R_EL1 register value.
Replace this with symbolic names to allow reusing them later.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 26c6a777

drivers/irqchip/irq-gic-v3.c

+9 −5
Original line number Diff line number Diff line
@@ -474,15 +474,19 @@ out: 
	return tlist;

}



#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \

	(MPIDR_AFFINITY_LEVEL(cluster_id, level) \

		<< ICC_SGI1R_AFFINITY_## level ##_SHIFT)



static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)

{

	u64 val;



	val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48	|

	       MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32	|

	       irq << 24			    		|

	       MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16	|

	       tlist);

	val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3)	|

	       MPIDR_TO_SGI_AFFINITY(cluster_id, 2)	|

	       irq << ICC_SGI1R_SGI_ID_SHIFT		|

	       MPIDR_TO_SGI_AFFINITY(cluster_id, 1)	|

	       tlist << ICC_SGI1R_TARGET_LIST_SHIFT);



	pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);

	gic_write_sgi1r(val);

include/linux/irqchip/arm-gic-v3.h

+12 −0
Original line number Diff line number Diff line
@@ -142,6 +142,18 @@ 
#define ICC_SRE_EL2_SRE			(1 << 0)

#define ICC_SRE_EL2_ENABLE		(1 << 3)



#define ICC_SGI1R_TARGET_LIST_SHIFT	0

#define ICC_SGI1R_TARGET_LIST_MASK	(0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)

#define ICC_SGI1R_AFFINITY_1_SHIFT	16

#define ICC_SGI1R_AFFINITY_1_MASK	(0xff << ICC_SGI1R_AFFINITY_1_SHIFT)

#define ICC_SGI1R_SGI_ID_SHIFT		24

#define ICC_SGI1R_SGI_ID_MASK		(0xff << ICC_SGI1R_SGI_ID_SHIFT)

#define ICC_SGI1R_AFFINITY_2_SHIFT	32

#define ICC_SGI1R_AFFINITY_2_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)

#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT	40

#define ICC_SGI1R_AFFINITY_3_SHIFT	48

#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)



/*

 * System register definitions

 */